coreboot/src/southbridge/intel
Kyösti Mälkki ee253069a3 UPSTREAM: intel/i945: Use romstage_handoff for S3
Don't use scratchpad registers when we have romstage_handoff
to pass S3 resume flag. Scratchpad register was read too
late in ramstage so acpi_is_wakeup_s3() did not evaluate
correctly.

This fixes low memory corruption at 0x1000-0x102c and the lack
of coreboot tables (util/cbmem not working) after S3 resume.

This also fixes console log from reporting early in ramstage
"Normal boot" while on "S3 resume" path.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17675
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I2922a15a90d2f8272c3482579bdd96f8f33e9705
Reviewed-on: https://chromium-review.googlesource.com/419616
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-13 17:49:07 -08:00
..
bd82x6x UPSTREAM: buildsystem: Drop explicit (k)config.h includes 2016-12-09 03:29:54 -08:00
common UPSTREAM: intel PCI ops: Remove explicit PCI MMCONF access 2016-12-08 12:31:05 -08:00
fsp_bd82x6x UPSTREAM: intel PCI ops: Remove explicit PCI MMCONF access 2016-12-08 12:31:10 -08:00
fsp_i89xx UPSTREAM: intel PCI ops: Remove explicit PCI MMCONF access 2016-12-08 12:31:10 -08:00
fsp_rangeley UPSTREAM: intel PCI ops: Remove explicit PCI MMCONF access 2016-12-08 12:31:05 -08:00
i3100 UPSTREAM: sb/intel/i3100/lpc.c: Use tab for indents 2016-11-30 02:53:37 -08:00
i82371eb UPSTREAM: southbridge/intel/i82371eb: transition away from device_t 2016-09-13 22:19:42 -07:00
i82801ax UPSTREAM: southbridge/intel/i82801ax: transition away from device_t 2016-09-13 22:19:44 -07:00
i82801bx tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
i82801dx UPSTREAM: x86 SMM: Fix use with RELOCATABLE_RAMSTAGE 2016-12-13 17:48:57 -08:00
i82801ex UPSTREAM: src/southbridge: Code formating 2016-09-04 19:36:57 -07:00
i82801gx UPSTREAM: intel/i945: Use romstage_handoff for S3 2016-12-13 17:49:07 -08:00
i82801ix UPSTREAM: intel/gm45: Use romstage_handoff for S3 2016-12-13 17:49:04 -08:00
i82870 UPSTREAM: src/southbridge: Code formating 2016-09-04 19:36:57 -07:00
ibexpeak UPSTREAM: intel PCI ops: Remove explicit PCI MMCONF access 2016-12-08 12:31:05 -08:00
lynxpoint UPSTREAM: PCI ops: Define read-modify-write routines globally 2016-12-08 12:31:12 -08:00