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coreboot/include/arch/x86
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Ronald G. Minnich 979bdb5ed0 Add functions to print routes. 
I am totally convinced these are right. I am going on travel for a week 
and want these in your hands. 

Carl-Daniel as acked these, but for lack of time to get firefox going 
right now, 

Current serengeti output
DRAM(40)01000000-00ffffff, ->(1), R, W, 2 nodes, 1
DRAM(48)01000000-00ffffff, ->(1), R, W, 2 nodes, 1
DRAM(50)01000000-00ffffff, ->(1), R, W, 2 nodes, 1
DRAM(58)01000000-00ffffff, ->(1), R, W, 2 nodes, 1
DRAM(60)00000000-00ffffff, ->(4), , , No interleave, 0
DRAM(68)00000000-00ffffff, ->(0), R, W, 8 nodes, 0
DRAM(70)00000000-00ffffff, ->(0), , , No interleave, 0
DRAM(78)00000000-00ffffff, ->(0), , , No interleave, 0
MMIO(80)01a00000-1100ffff, ->(0,2), , , CPU disable 0, Lock 0, Non 
posted 0
MMIO(88)75060000-0000ffff, ->(2,0), , , CPU disable 0, Lock 0, Non 
posted 0
MMIO(90)51040000-3f00ffff, ->(0,0), , , CPU disable 1, Lock 0, Non 
posted 0
MMIO(98)00000000-0000ffff, ->(0,0), R, W, CPU disable 0, Lock 0, Non 
posted 0
MMIO(a0)01c00000-1100ffff, ->(0,1), , , CPU disable 0, Lock 0, Non 
posted 1
MMIO(a8)75000000-0000ffff, ->(2,0), , , CPU disable 0, Lock 0, Non 
posted 0
MMIO(b0)51040000-0000ffff, ->(0,0), , , CPU disable 1, Lock 0, Non 
posted 0
MMIO(b8)00000000-0000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non 
posted 0
PCIIO(c0)00001010-00003110, ->(0,1), , ,VGA 0 ISA 0
PCIIO(c8)00000750-00000000, ->(2,0), , ,VGA 0 ISA 1
PCIIO(d0)00002510-00000000, ->(0,0), , ,VGA 1 ISA 0
PCIIO(d8)00000000-00000000, ->(0,0), , ,VGA 0 ISA 0
CONFIG(e0)00000000-00000000 ->(0,0),  CE 0
CONFIG(e4)00000000-00000000 ->(0,0),  CE 0
CONFIG(e8)00000000-00000000 ->(0,0),  CE 0
CONFIG(ec)00000000-00000000 ->(0,0),  CE 0

Either the DRAM output is wrong or there is a real problem with our 
DRAM programming. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@941 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-21 03:20:05 +00:00
..
amd/k8 Add functions to print routes. 2008-10-21 03:20:05 +00:00
arch Now version 3: LinuxBIOS -> coreboot rename. 2008-01-27 18:54:57 +00:00
amd_geodelx.h Documentation improvement for sys_info. 2008-08-28 01:31:24 +00:00
byteorder.h Use the same naming convention and placement for "include guards" in 2007-05-21 06:48:47 +00:00
cpu.h We need a way to find out where our stack and our global variables are 2008-10-16 03:03:33 +00:00
div64.h Now version 3: LinuxBIOS -> coreboot rename. 2008-01-27 18:54:57 +00:00
io.h Use the same naming convention and placement for "include guards" in 2007-05-21 06:48:47 +00:00
lapic.h This is closer! There are < 10 functions to be worked out, so most of 2008-08-29 04:33:56 +00:00
lapic_def.h Add lapic defines and support. 2008-08-11 23:02:34 +00:00
legacy.h Now version 3: LinuxBIOS -> coreboot rename. 2008-01-27 18:54:57 +00:00
macros.h Minor cosmetic and/or license header fixes (trivial). 2008-08-11 21:01:54 +00:00
msr.h A lot of the v3 header files require other header files to be #included 2008-02-19 00:34:32 +00:00
mtrr.h The m57sli almost builds. It's pretty empty. The dtc is not run . 2008-08-01 17:03:22 +00:00
multiboot.h Signed-off-by: Robert Millan <rmh@aybabtu.com> 2008-09-24 14:54:33 +00:00
pci_ops.h Console: 2008-08-09 21:03:57 +00:00
pciconf.h Remove dead code protected by #if 0 since it appeared. 2008-02-15 23:58:09 +00:00
pirq_routing.h Minor cosmetic and/or license header fixes (trivial). 2008-08-11 21:01:54 +00:00
qemu.h Fix for globals for qemu. 2008-08-28 02:32:27 +00:00
stage1.h Right now we face the problem that we can't support processors which 2008-10-16 03:00:28 +00:00
swab.h Now version 3: LinuxBIOS -> coreboot rename. 2008-01-27 18:54:57 +00:00
types.h Use the same naming convention and placement for "include guards" in 2007-05-21 06:48:47 +00:00
via_c7.h Add the last bits to support C7 in v3 2008-10-12 00:51:10 +00:00