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coreboot/src/soc
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Matt DeVillier 96a7d9e76b soc/intel/cannonlake: Add missing entry to soc_acpi_name() 
The device name for the SA thermal/DPTF PCI device was missing from
soc_acpi_name(), leading to an invalid PLI device constraint entry
being generated in the SSDT (the name field was blank/missing).
Add the missing entry, matching the name to the existing ACPI
device.

TEST=build/boot Win11 on google/puff (wyvern) without a BSOD.

Change-Id: I7ac03fd292246981f32d9ad894b8f0f9870240fc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78869
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-11-03 15:33:21 +00:00
..
amd soc/amd/*: Ensure PSP soft fuse bitmask set properly 2023-11-02 13:57:18 +00:00
cavium soc/cavium/cn81xx/bootblock_custom.S: Specify arch 2023-10-20 14:30:54 +00:00
example/min86 soc: Remove SOC_SPECIFIC_OPTIONS 2023-08-21 23:45:43 +00:00
intel soc/intel/cannonlake: Add missing entry to soc_acpi_name() 2023-11-03 15:33:21 +00:00
mediatek device/device.h: Rename pci_domain_scan_bus 2023-10-20 14:24:57 +00:00
nvidia memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere 2023-10-11 12:08:22 +00:00
qualcomm device/device.h: Rename pci_domain_scan_bus 2023-10-20 14:24:57 +00:00
rockchip memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere 2023-10-11 12:08:22 +00:00
samsung memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere 2023-10-11 12:08:22 +00:00
sifive/fu540 memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere 2023-10-11 12:08:22 +00:00
ti src/soc/ti: Remove unnecessary space after casts 2022-11-22 13:42:28 +00:00
ucb/riscv cbmem_top_chipset: Change the return value to uintptr_t 2022-11-18 16:00:45 +00:00