coreboot/src
Philipp Hug 968a23d2e0 riscv: fix non-SMP support
Use CONFIG_CPU_MAX which defaults to 1 instead of CONFIG_RISCV_HART_NUM.
The default value of CONFIG_RISCV_HART_NUM was 0 and cause a jump to address 0.
Add a die() call to fail gracefully.

Change-Id: I4e3aa09b787ae0f26a4aae375f4e5fcd745a0a1e
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/c/29993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Xiang Wang <wxjstz@126.com>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-12-07 11:37:53 +00:00
..
acpi arch/x86: Add common AMD ACPI hardware definitions 2017-11-10 19:15:38 +00:00
arch riscv: fix non-SMP support 2018-12-07 11:37:53 +00:00
commonlib src: Remove duplicated round up function 2018-11-29 12:17:45 +00:00
console (console,drivers/uart)/Kconfig: Fix dependencies 2018-11-21 22:49:48 +00:00
cpu cpu/x86/pae: Fix pointer casts 2018-12-05 16:57:15 +00:00
device arch/power8: Rename to ppc64 2018-11-30 20:02:17 +00:00
drivers drivers/i2c/designware: Add soc_clock entry for 216MHz 2018-12-07 11:18:55 +00:00
ec lenovo/h8,thinkpads: Re-do USB Always On 2018-12-06 11:59:22 +00:00
include smmstore: make smmstore's SMM handler code follow everything else 2018-12-05 13:31:22 +00:00
lib cbfs: Alert if something goes wrong in cbfs_boot_locate() 2018-12-07 11:34:54 +00:00
mainboard mainboard/lenovo/t430s: Add ThinkPad T431s as a variant 2018-12-07 11:20:53 +00:00
northbridge nb/intel/gm45: Make fetching the blc_pwm freq global 2018-12-03 13:03:13 +00:00
security tss: implement tlcl_save_state 2018-11-28 18:32:59 +00:00
soc riscv: fix non-SMP support 2018-12-07 11:37:53 +00:00
southbridge sb/amd/pi/hudson: Fix UART address math 2018-12-07 11:34:13 +00:00
superio src: Add required space after "switch" 2018-11-19 08:17:06 +00:00
vendorcode vendorcode/cavium: Supply bdk_pop and bdk_dpop definitions 2018-11-28 11:47:59 +00:00
Kconfig cpu/x86/Kconfig.debug: Move more options here 2018-11-23 08:38:31 +00:00