Arthur Heymans 97c7c6bbb6 cpu/intel/model_2065x: Put stage cache in TSEG ... TSEG is not accessible in ring 0 after it is locked in ramstage, in contrast with cbmem which remains accessible. Assuming SMM does not touch the cache this is a good region to cache stages. Change-Id: I89cbfb6ece62f554ac676fe686115e841d2c1e40 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>		2019-05-27 17:25:57 +00:00
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amd	AGESA binaryPI: Add AGESA entry timestamps	2019-05-25 08:39:05 +00:00
intel	cpu/intel/model_2065x: Put stage cache in TSEG	2019-05-27 17:25:57 +00:00
via/vx900	northbridge/via/vx900: Remove unused variables	2019-04-25 15:54:24 +00:00