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coreboot/src/cpu/intel/haswell
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Arthur Heymans 4513020064 cpu/intel: Use the common code to initialize the romstage timestamps 
The initial timestamps are now pushed on the stack when entering the
romstage C code.

Tested on Asus P5QC.

Change-Id: I88e972caafff5c53d8e68e85415f920c7341b92d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-09 09:56:06 +00:00
..
acpi.c cpu/intel/haswell: Rework acpi/cpu.asl 2018-11-30 21:52:00 +00:00
bootblock.c src: Remove unneeded include "{arch,cpu}/cpu.h" 2018-11-12 09:22:18 +00:00
chip.h tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
finalize.c src: Remove unneeded include "{arch,cpu}/cpu.h" 2018-11-12 09:22:18 +00:00
haswell.h src: Move common IA-32 MSRs to <cpu/x86/msr.h> 2018-10-11 21:06:53 +00:00
haswell_init.c cpu/intel/common: decouple IA32_FEATURE_CONTROL lock from set_vmx() 2018-12-20 22:18:05 +00:00
Kconfig arch/x86: SSE2 implies SSE support 2018-12-28 06:41:29 +00:00
Makefile.inc cpu/intel/haswell: Allow use of TSC for the monotonic timer 2018-11-01 22:22:57 +00:00
monotonic_timer.c tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
romstage.c cpu/intel: Use the common code to initialize the romstage timestamps 2019-01-09 09:56:06 +00:00
smmrelocate.c device: Use pcidev_on_root() 2019-01-06 01:17:54 +00:00
stage_cache.c src/cpu: Capitalize ROM and RAM 2016-07-31 18:28:27 +02:00
tsc_freq.c tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00