Shelley Chen 3cce7a0311 soc/intel/cannonlake: Add field to identify single channel memory ... Variants of Hatch need to accommodate single channel DDR. Also, removing const modifier as we'll need to set these fields incrementally now. For the single channel configuration, we set MemorySpdPtr10 to 0. For the dual channel configuration, we set MemorySpdPtr10 to MemorySpdPtr00. BUG=b:123062346, b:122959294 BRANCH=None TEST=Boot into current boards and ensure that we have 2 channels as expected Change-Id: Ice22b103664187834e255d1359bfd9b51993b5b6 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/31262 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2019-02-21 11:31:19 +00:00
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amd	soc/amd/common: Move PI refcode loader	2019-02-15 17:49:31 +00:00
cavium	bootmem: add new memory type for BL31	2019-02-05 13:41:45 +00:00
imgtec	(console,drivers/uart)/Kconfig: Fix dependencies	2018-11-21 22:49:48 +00:00
intel	soc/intel/cannonlake: Add field to identify single channel memory	2019-02-21 11:31:19 +00:00
mediatek	bootmem: add new memory type for BL31	2019-02-05 13:41:45 +00:00
nvidia	bootmem: add new memory type for BL31	2019-02-05 13:41:45 +00:00
qualcomm	console: Change BOOTBLOCK_CONSOLE default to y	2019-01-14 12:13:55 +00:00
rockchip	bootmem: add new memory type for BL31	2019-02-05 13:41:45 +00:00
samsung	src: Don't use a #defines like Kconfig symbols	2019-01-28 13:41:28 +00:00
sifive	riscv: ARCH_RISCV_RV{32,64} selects ARCH_RISCV	2019-01-24 14:21:01 +00:00
ucb	riscv: Add initial support for 32bit boards	2019-02-13 04:49:14 +00:00