716738a6b8
There are some boards that do a significant amount of work after cache-as-ram is torn down but before ramstage is loaded. For example, using vboot to verify the ramstage is one such operation. However, there are pieces of code that are executed that reference global variables that are linked in the cache-as-ram region. If those variables are referenced after cache-as-ram is torn down then the values observed will most likely be incorrect. Therefore provide a Kconfig option to select cache-as-ram migration to memory using cbmem. This option is named CAR_MIGRATION. When enabled, the address of cache-as-ram variables may be obtained dynamically. Additionally, when cache-as-ram migration occurs the cache-as-ram data region for global variables is copied into cbmem. There are also automatic callbacks for other modules to perform their own migration, if necessary. Change-Id: I2e77219647c2bd2b1aa845b262be3b2543f1fcb7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/3232 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
126 lines
2.5 KiB
Text
126 lines
2.5 KiB
Text
config SERIAL_CPU_INIT
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bool
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default y
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config UDELAY_IO
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bool
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default y if !UDELAY_LAPIC && !UDELAY_TSC && !UDELAY_TIMER2
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default n
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config UDELAY_LAPIC
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bool
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default n
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config LAPIC_MONOTONIC_TIMER
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def_bool n
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depends on UDELAY_LAPIC
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select HAVE_MONOTONIC_TIMER
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help
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Expose monotonic time using the local apic.
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config UDELAY_LAPIC_FIXED_FSB
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int
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config UDELAY_TSC
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bool
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default n
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config TSC_CONSTANT_RATE
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def_bool n
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depends on UDELAY_TSC
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help
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This option asserts that the TSC ticks at a known constant rate.
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Therefore, no TSC calibration is required.
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config TSC_MONOTONIC_TIMER
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def_bool n
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depends on UDELAY_TSC
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select HAVE_MONOTONIC_TIMER
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help
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Expose monotonic time using the TSC.
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config UDELAY_TIMER2
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bool
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default n
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config TSC_CALIBRATE_WITH_IO
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bool
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default n
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config TSC_SYNC_LFENCE
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bool
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default n
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help
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The CPU driver should select this if the CPU needs
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to execute an lfence instruction in order to synchronize
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rdtsc. This is true for all modern AMD CPUs.
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config TSC_SYNC_MFENCE
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bool
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default n
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help
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The CPU driver should select this if the CPU needs
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to execute an mfence instruction in order to synchronize
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rdtsc. This is true for all modern Intel CPUs.
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config XIP_ROM_SIZE
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hex
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default ROM_SIZE if ROMCC
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default 0x10000
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config CPU_ADDR_BITS
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int
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default 36
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config LOGICAL_CPUS
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bool
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default y
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config CACHE_ROM
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bool "Allow for caching system ROM."
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default n
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help
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When selected a variable range MTRR is allocated for coreboot and
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the bootloader enables caching of the system ROM for faster access.
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config SMM_TSEG
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bool
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default n
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config SMM_TSEG_SIZE
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hex
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default 0
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config SMM_MODULES
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bool
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default n
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depends on HAVE_SMI_HANDLER
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select RELOCATABLE_MODULES
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help
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If SMM_MODULES is selected then SMM handlers are built as modules.
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A SMM stub along with a SMM loader/relocator. All the handlers are
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written in C with stub being the only assembly.
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config SMM_MODULE_HEAP_SIZE
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hex
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default 0x4000
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depends on SMM_MODULES
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help
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This option determines the size of the heap within the SMM handler
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modules.
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config X86_AMD_FIXED_MTRRS
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bool
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default n
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help
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This option informs the MTRR code to use the RdMem and WrMem fields
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in the fixed MTRR MSRs.
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config CAR_MIGRATION
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def_bool n
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depends on DYNAMIC_CBMEM || EARLY_CBMEM_INIT
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help
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Migrate the cache-as-ram variables to CBMEM once CBMEM is set up
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in romstage. This option is only needed if one will be doing more
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work in romstage after the cache-as-ram is torn down aside from
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loading ramstage.
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