Subrata Banik 9355f318fa soc/intel/cmn/ramtop: Refactor MTRR handling for RAMTOP range ... This patch refactors RAMTOP MTRR type selection to address a critical NEM logic bug on SoCs with non-power-of-two cache sets. This bug can cause runtime hangs when Write Back (WB) caching is enabled. Workaround: Force MTRR type to WC (Write Combining) on affected SoCs when the cache set count is not a power of two. BUG=b:306677879 BRANCH=firmware-rex-15709.B TEST=Verified boot on google/ovis and google/rex (including Ovis with non-power-of-two cache configuration). Change-Id: Ia9a8f0d37d581b05c19ea7f9b1a07933caa956d4 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81269 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2024-03-17 11:55:08 +00:00
..
amd	soc/amd: move common pci_domain_fill_ssdt implementation to acpi/	2024-02-29 15:39:06 +00:00
cavium	soc: Add SPDX license headers to Kconfig files	2024-02-18 02:03:37 +00:00
example/min86	soc: Add SPDX license headers to Kconfig files	2024-02-18 02:03:37 +00:00
intel	soc/intel/cmn/ramtop: Refactor MTRR handling for RAMTOP range	2024-03-17 11:55:08 +00:00
mediatek	treewide: Move stdlib.h to commonlib	2024-03-15 10:09:43 +00:00
nvidia	soc: Add SPDX license headers to Kconfig files	2024-02-18 02:03:37 +00:00
qualcomm	soc: Add SPDX license headers to Kconfig files	2024-02-18 02:03:37 +00:00
rockchip	soc: Add SPDX license headers to Kconfig files	2024-02-18 02:03:37 +00:00
samsung	soc: Add SPDX license headers to Kconfig files	2024-02-18 02:03:37 +00:00
sifive	soc/sifive/fu740: Add FU740 SOC	2024-03-03 21:20:03 +00:00
ti	soc: Add SPDX license headers to Kconfig files	2024-02-18 02:03:37 +00:00
ucb/riscv	soc: Add SPDX license headers to Kconfig files	2024-02-18 02:03:37 +00:00