Hannah Williams 92e3aaf467 UPSTREAM: soc/intel/apollolake: Include _PTS, _WAK and _SWS ... Change-Id: I3400611095978421c7b35a7ea9c68b8571942ae9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15138 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/356446 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org>		2016-06-27 17:12:48 -07:00
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apollolake	UPSTREAM: soc/intel/apollolake: Include _PTS, _WAK and _SWS	2016-06-27 17:12:48 -07:00
baytrail	UPSTREAM: Ignore RAMTOP for MTRRs	2016-06-22 10:41:48 -07:00
braswell	soc/intel: indicate to build system that XIP_ROM_SIZE isn't used	2016-05-06 16:50:00 +02:00
broadwell	UPSTREAM: Ignore RAMTOP for MTRRs	2016-06-22 10:41:48 -07:00
common	UPSTREAM: soc/intel/common/acpi: Add _PTS, _WAK methods	2016-06-23 00:58:52 -07:00
fsp_baytrail	UPSTREAM: intel/fsp_baytrail/i2c: mask i2c interrupts in i2c_init()	2016-06-03 08:55:13 -07:00
fsp_broadwell_de	soc/intel/fsp_broadwell_de: convert to using common MP init	2016-05-06 16:41:01 +02:00
quark	UPSTREAM: soc/intel/quark: Add C bootblock	2016-06-13 15:56:07 -07:00
sch	UPSTREAM: intel/sch: Merge northbridge and southbridge in src/soc	2016-05-20 17:08:20 -07:00
skylake	UPSTREAM: intel/skylake: Run spi_init as early as possible in ramstage	2016-06-22 10:41:15 -07:00