coreboot/src
Elyes Haouas 92d77dd2e3 spd_bin.h: Deduplicate SPD definitions
Use already defined macros in `spd.h`, ddr3.h`and `ddr4.h`.

TEST=Built google/cyan (Cyan) with BUILD_TIMELESS=1, no change in output
ROM.

Change-Id: I727aa38236ad97f9c529389fdb7d7d11c1db08d0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82314
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-03-16 05:25:07 +00:00
..
acpi src/acpigen: support 0-initialized buffer in acpigen_write_byte_buffer 2025-03-05 16:44:43 +00:00
arch arch/riscv: Add common FDT build 2025-02-14 17:11:19 +00:00
commonlib {commonlib, lib}: Rename CBMEM_ID_FSP_LOGO to CBMEM_ID_BMP_LOGO 2025-03-06 19:02:27 +00:00
console console/i2c_smbus: Allow to send data w/o register offset 2024-07-11 00:06:22 +00:00
cpu cpu/intel/haswell: Usee boolean for haswell_is_ult() 2025-03-03 01:15:17 +00:00
device device/pci_device: Move PCI Option ROM code into pci_rom.c 2025-03-10 11:35:57 +00:00
drivers drivers/intel/touch: Add Intel Touch Controller driver 2025-03-14 16:25:19 +00:00
ec ec/google/chromeec: Override Lid State for Factory Netboot 2025-03-13 19:23:00 +00:00
include spd_bin.h: Deduplicate SPD definitions 2025-03-16 05:25:07 +00:00
lib spd_bin.h: Deduplicate SPD definitions 2025-03-16 05:25:07 +00:00
mainboard spd_bin.h: Deduplicate SPD definitions 2025-03-16 05:25:07 +00:00
northbridge haswell NRI: Do sense amplifier offset training 2025-03-08 22:55:39 +00:00
sbom
security drivers/pc80/tpm: Remove flag TPM_RDRESP_NEED_DELAY 2024-10-14 15:26:11 +00:00
soc spd_bin.h: Deduplicate SPD definitions 2025-03-16 05:25:07 +00:00
southbridge haswell NRI: Add DDR3 JEDEC reset and init 2025-03-08 22:53:24 +00:00
superio superio/ite: Add support for IT8625E 2024-11-21 15:49:12 +00:00
vendorcode vc/intel/fsp/ptl: Update header files from 3015_00 to 3071_00 2025-03-12 05:00:04 +00:00
Kconfig Kconfig: Update prompt and help text for CBFS_SIZE 2025-03-01 23:29:09 +00:00