coreboot/src/cpu
Marc Jones d8d8c63cf7 Fix MTRR TOM2 WB cache setup for AMD CPUs > revF.
The MTRR check for WB TOM2 setting was only checking revF, not extended family
revisions. All families above revf indicate 0xf in the family field and have
additional bits in the extended family field.

Change-Id: I93d719789acda6b7c42de7fd6d4bad2da866a25f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/627
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-20 05:37:26 +01:00
..
amd Fix MTRR TOM2 WB cache setup for AMD CPUs > revF. 2012-02-20 05:37:26 +01:00
intel Intel cpus: use CPU_PHYSMASK_HI define in CAR 2012-02-16 01:55:50 +01:00
via Remove whitespace. 2012-02-17 19:04:31 +01:00
x86 Remove whitespace. 2012-02-17 19:04:31 +01:00
Kconfig
Makefile.inc