coreboot/src
Shilpa Sreeramalu 91a192f6d0 intel/kunimitsu: Enable and support for DPTF
This patch includes the DPTF specific ASL files in the main
DSDT definition and enables the CPU thermal participant device
in the device tree. It also enables the DPTF flag in the global
NVS table.It also adds the ASL settings specfic to the mainboard.

BRANCH=None
BUG=chrome-os-partner:40855
TEST=Built for kunimitsu board. Tested to see that the thermal devices
and the participants are enumerated and can be seen in the
/sys/bus/platform/devices. Also checked the temperature readings of the
cooling devices and the thermal zones enumerated in the /sys/class/thermal.

Change-Id: I5fb28e4480648eab39cc9b13ed55eae1d3db4d42
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 54f7f33a12eb5744d6108e362fa1d078fe838b3c
Original-Change-Id: I82527989919bd4f3c49fb58dfc9463f1c1bd3353
Original-Signed-off-by: Shilpa Sreeramalu <shilpa.sreeramalu@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/284821
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294650
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch@intel.com>
Reviewed-on: http://review.coreboot.org/11429
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29 07:31:39 +00:00
..
acpi acpi/sata: add generic sata ssdt port generator 2015-06-07 01:24:47 +02:00
arch arm64: xcompile: Add support for A53 erratum 843419 2015-08-28 06:46:09 +00:00
console consoles: remove unused infrastructure 2015-05-26 19:02:54 +02:00
cpu Intel: Remove CACHE_MRC_BIN - 'selected' everywhere in Kconfig 2015-08-25 17:36:45 +00:00
device x86 realmode: Set up the 8254 timer before running option rom 2015-07-16 04:03:45 +02:00
drivers intel/fsp1_1/hob.c: Refactor file to match coreboot coding style 2015-08-29 04:19:50 +00:00
ec chromeec: Add helper function to read EC switch state 2015-08-27 14:18:38 +00:00
include edid: add function to manually specify mode 2015-08-28 06:42:25 +00:00
lib edid: fix know_modes timing error 2015-08-28 06:44:20 +00:00
mainboard intel/kunimitsu: Enable and support for DPTF 2015-08-29 07:31:39 +00:00
northbridge edid: Use edid_mode struct to reduce redundancy 2015-08-28 06:42:03 +00:00
soc intel/skylake: remove the gpio_fsp.h usage as skylake boards move gpio 2015-08-29 07:26:30 +00:00
southbridge AMD ROMSIG: Only check location if ROMSIG is used 2015-08-19 01:26:42 +00:00
superio superio/smsc: Add support for SMSC DME1737 2015-07-13 17:11:00 +02:00
vendorcode Chromeos: Remove Kconfig workaround for VIRTUAL_DEV_SWITCH warnings 2015-08-26 15:46:09 +00:00
Kconfig skylake: remove CBFS_SIZE option in SoC directory 2015-08-13 16:11:58 +02:00