Felix Held 4e379a2374 soc/amd: make configure_espi_with_mb_hook call conditional ... If a system doesn't use eSPI or has the eSPI interface already configured in verstage on PSP, not calling configure_espi_with_mb_hook from fch_pre_init makes it a bit more obvious that the eSPI interface initialization will be skipped. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia77b83d56a5dab1bac6cfbbd92d33aa60a9e8b89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>		2021-10-15 20:04:44 +00:00
..
acpi	soc/amd/cezanna/acpi/mmio.asl: enable ACPI AOAC for I2C	2021-09-20 12:56:21 +00:00
include/soc	soc/amd/common/block/i2c: implement proper read_resource	2021-10-15 19:18:26 +00:00
psp_verstage	soc/amd/cezanne, vc/amd/fsp/*: Add support for CCP DMA SVC call	2021-09-27 13:29:37 +00:00
acpi.c	soc/amd/cezanne: add ACPI CPPC support for AMD	2021-07-15 21:39:04 +00:00
agesa_acpi.c	soc/amd/cezanne: Generate IVRS for cezanne	2021-08-05 15:54:50 +00:00
aoac.c	soc/amd/cezanne: factor out AOAC offset defines	2021-06-16 16:38:25 +00:00
bootblock.c	soc/amd/common/block/espi_util: Refactor eSPI Setup	2021-10-13 17:37:39 +00:00
chip.c	soc/amd/cezanne/chip: add functionality to power down eMMC interface	2021-08-29 20:58:51 +00:00
chip.h	soc/amd/*/chip.h: Correct PSPP Enum Value	2021-07-24 19:49:45 +00:00
chipset.cb	soc/amd/cezanne/chip: add functionality to power down eMMC interface	2021-08-29 20:58:51 +00:00
config.c
cppc.c	soc/amd/cezanne,soc/intel/common: rework CPPC table generation	2021-10-13 13:51:24 +00:00
cpu.c	soc/amd: move check_mca prototype to soc/amd/common/blocks/include	2021-07-14 21:58:59 +00:00
data_fabric.c	cpu/x86/lapic: Replace LOCAL_APIC_ADDR references	2021-06-11 07:11:43 +00:00
early_fch.c	soc/amd: make configure_espi_with_mb_hook call conditional	2021-10-15 20:04:44 +00:00
fch.c	src/soc/amd/cezanne: enable clock gating	2021-10-13 22:01:52 +00:00
fsp_m_params.c	soc/amd/cezanne/fsp_m_params: use DEV_PTR to check if device is enabled	2021-09-21 13:56:26 +00:00
fsp_s_params.c	soc/amd/{common,cezanne}: Implement HAVE_PAYLOAD_PRELOAD_CACHE	2021-07-19 14:58:53 +00:00
fw.cfg	soc/amd/cezanne: Add PSP whitelist debug unlock support	2021-03-01 08:27:57 +00:00
gpio.c	soc/amd/common/blocks/include: rename gpio_banks.h to gpio.h	2021-09-23 18:33:00 +00:00
graphics.c	soc/amd/cezanne/graphics: add VBIOS ID remapping for Barcelo	2021-07-17 21:32:59 +00:00
i2c.c	soc/amd/cezanne: Configure I2C Pad RX Select through devicetree	2021-06-07 05:18:49 +00:00
Kconfig	Revert "soc/amd/cezanne: Disable Co-op multitasking"	2021-10-05 22:39:38 +00:00
Makefile.inc	soc/amd/cezanne/makefile: order source files alphabetically	2021-07-20 13:33:28 +00:00
mca.c	soc/amd/cezanne/mca: add and use mca_bank_name[]	2021-07-21 22:38:11 +00:00
reset.c	soc/amd/cezanne: remove warm reset flag code	2021-06-11 21:48:28 +00:00
romstage.c	soc/amd/cezanne: Move APOB update into ramstage	2021-07-14 17:54:36 +00:00
root_complex.c	soc/amd: factor out acpigen_write_alib_dptc to common code	2021-05-13 00:58:26 +00:00
smihandler.c	soc/amd/cezanne/smihandler: add ELOG and SMMSTORE support	2021-03-10 00:30:15 +00:00
smu.c	soc/amd/cezanne: add SMU support	2021-03-04 19:55:27 +00:00
uart.c	soc/amd/cezanne,picasso/uart: implement read_resource	2021-10-15 14:46:58 +00:00
xhci.c	soc/amd/common/blocks/include: rename gpio_banks.h to gpio.h	2021-09-23 18:33:00 +00:00