2b77f8a498
On x86 systems there is a concept of cachings the ROM. However, the typical policy is that the boot cpu is the only one with it enabled. In order to ensure the MTRRs are the same across cores the rom cache needs to be disabled prior to OS resume or boot handoff. Therefore, utilize the boot state callbacks to schedule the disabling of the ROM cache at the ramstage exit points. Change-Id: If67b9b50081d21d505685a96d201c242e71b64f7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49746 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
25 lines
739 B
C
25 lines
739 B
C
#ifndef CPU_CPU_H
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#define CPU_CPU_H
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#include <arch/cpu.h>
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#if !defined(__PRE_RAM__) && !defined(__SMM__)
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void cpu_initialize(unsigned int cpu_index);
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struct bus;
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void initialize_cpus(struct bus *cpu_bus);
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void asmlinkage secondary_cpu_init(unsigned int cpu_index);
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#if CONFIG_HAVE_SMI_HANDLER
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void smm_init(void);
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void smm_lock(void);
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void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
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#endif
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#define __cpu_driver __attribute__ ((used,__section__(".rodata.cpu_driver")))
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/** start of compile time generated pci driver array */
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extern struct cpu_driver cpu_drivers[];
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/** end of compile time generated pci driver array */
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extern struct cpu_driver ecpu_drivers[];
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#endif /* !__PRE_RAM__ && !__SMM__ */
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#endif /* CPU_CPU_H */
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