Casper Chang 8fcefd3f6f soc/intel/alderlake: add MaxDramSpeed config ... This change add MaxDramSpeed for variants usage to config dram speed. Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: Iba0fae0ab4ff0121dc63af792458492eeb21ec2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>		2021-09-24 15:27:43 +00:00
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alderlake	soc/intel/alderlake: add MaxDramSpeed config	2021-09-24 15:27:43 +00:00
apollolake	vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main	2021-09-16 23:44:20 +00:00
baytrail	cpu/x86/tsc: Deduplicate Makefile logic	2021-09-08 14:35:16 +00:00
braswell	cpu/x86/tsc: Deduplicate Makefile logic	2021-09-08 14:35:16 +00:00
broadwell	soc/broadwell/acpi.c: Fix unresolvable symbol '\DNVS'	2021-09-15 15:28:57 +00:00
cannonlake	soc/intel/cannonlake: Switch to runtime generation of Intel Power Engine	2021-09-10 21:57:20 +00:00
common	soc/amd,intel/common/include/gpio: improve documentation of overrides	2021-09-23 14:41:30 +00:00
denverton_ns	cpu/x86/tsc: Deduplicate Makefile logic	2021-09-08 14:35:16 +00:00
elkhartlake	soc/intel/{xeon-sp,icl,tgl,jsl,ehl}: add NMI_{EN,STS} registers	2021-09-23 06:31:48 +00:00
icelake	soc/intel/icelake: correct wrong gpio SMI register base offsets	2021-09-23 06:31:58 +00:00
jasperlake	soc/intel/{xeon-sp,icl,tgl,jsl,ehl}: add NMI_{EN,STS} registers	2021-09-23 06:31:48 +00:00
quark	cpu/x86/tsc: Deduplicate Makefile logic	2021-09-08 14:35:16 +00:00
skylake	vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main	2021-09-16 23:44:20 +00:00
tigerlake	soc/intel/tgl: correct wrong gpio GPI enable register base offset	2021-09-23 06:32:11 +00:00
xeon_sp	soc/intel/xeon_sp/cpx: Use FSP repo	2021-09-23 06:38:52 +00:00
Kconfig