Shreesh Chhabbi 8fadf5aabf mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVP ... These changes are according to spd_binary_optimization_volteer_v0.4 sheet. Offset Current value Updated value Analysis 1 0x10 0x11 As per SPD spec rev 1.1 5 0x19 0x21 16 bits for Row addrs, 10 bits for Column addrs 6 0x95 0xB5 4 die, 2 ch per pkg, Byte 16 signal matrix 12 0x02 0x0A 2 ranks per ch, 16 bits device data width 18 0x05 0x04 4267MHz support 29 0x90 0xC0 HW specific 30 0x06 0x68 HW specific 31 0xD0 0x60 HW specific 32 0x02 0x04 HW specific 125 0x00 0xE1 4267MHz support BUG=b:159319534 TEST=Tested multiple cold boot cycles on TGL-UP3 with QS silicon Change-Id: Ie506fbfe86a3ffb77763e8d9ef7e8aa69ea44bd3 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42524 Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2020-08-31 06:45:04 +00:00
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acpi	src/acpi: Drop unneeded empty lines	2020-08-24 09:16:59 +00:00
arch	symbols: Change implementation details of DECLARE_OPTIONAL_REGION()	2020-08-27 22:11:17 +00:00
commonlib	src: Remove incorrect x86 exception not from TS_DONE_LOADING description	2020-08-28 06:07:37 +00:00
console	src: Remove unused 'include <stddef.h>	2020-08-18 12:15:44 +00:00
cpu	cpu/intel/haswell: Set LT_LOCK_MEMORY MSR on finalize step	2020-08-30 19:25:43 +00:00
device	{sb/intel/*/azalia.c,device/azalia_device.c}: Reduce differences	2020-08-17 06:58:45 +00:00
drivers	{intel/gma,include/device}: Delete unused 'drm_dp_helper.h' file	2020-08-31 06:36:18 +00:00
ec
include	include/device/azalia_device: Fix typo	2020-08-31 06:41:50 +00:00
lib	fw_config: Add caching to successfully probed fields	2020-08-31 06:38:09 +00:00
mainboard	mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVP	2020-08-31 06:45:04 +00:00
northbridge	nb/intel/sandybridge: Add ECC error injection register information	2020-08-31 06:28:09 +00:00
security	security/intel/txt/getsec.c: Do not check lock bit	2020-08-30 19:26:48 +00:00
soc	soc/amd/picasso/southbridge: make GPP clock outputs configurable	2020-08-31 06:42:39 +00:00
southbridge	sb/intel/bd82x6x: Factor out common ME functions	2020-08-29 20:15:37 +00:00
superio	superio/winbond/wpcd376i: Resurrect the driver	2020-08-31 06:29:47 +00:00
vendorcode	vendorcode/google: Add error handling	2020-08-31 06:28:45 +00:00
Kconfig	Kconfig: Update ASan config options	2020-08-21 07:42:21 +00:00