coreboot/src/arch
Ronald G. Minnich 8eed92ec3a UPSTREAM: RISCV: Clean up the common architectural code
This version of coreboot successfully starts a Harvey (Plan 9) kernel as a payload,
entering main() with no supporting assembly code for startup. The Harvey port
is not complete so it just panics but ... it gets started.

We provide a standard payload function that takes a pointer argument
and makes the jump from machine to supervisor mode;
the days of kernels running in machine mode are over.

We do some small tweaks to the virtual memory code. We temporarily
disable two functions that won't work on some targets as register
numbers changed between 1.7 and 1.9. Once lowrisc catches up
we'll reenable them.

We add the PAGETABLES to the memlayout.ld and use _pagetables in the virtual
memory setup code.

We now use the _stack and _estack from memlayout so we know where things are.
As time goes on maybe we can kill all the magic numbers.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/17058
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>

Change-Id: I6caadfa9627fa35e31580492be01d4af908d31d9
Reviewed-on: https://chromium-review.googlesource.com/402383
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-24 23:31:14 -07:00
..
arm UPSTREAM: src/arch: Improve code formatting 2016-09-13 22:20:24 -07:00
arm64 UPSTREAM: src/arch: Improve code formatting 2016-09-13 22:20:24 -07:00
mips build system: remove CBFSTOOL_PRE1_OPTS 2016-05-03 11:40:49 +02:00
power8 UPSTREAM: region: Add writeat and eraseat support 2016-06-27 17:13:18 -07:00
riscv UPSTREAM: RISCV: Clean up the common architectural code 2016-10-24 23:31:14 -07:00
x86 UPSTREAM: arch/x86/acpigen: Add support for interacting with GPIOs 2016-10-24 23:31:11 -07:00