8eb19fcf42
Program PIRQ Routing with correct values, as done by FSP, and also in 'soc/intel/skylake/romstage/pch.c' file. If not done, these values get overridden by "0" during PxRC -> PIRQ programming in ramstage, in 'soc/intel/skylake/lpc.c' file pch_pirq_init()function. BUG=none BRANCH=none TEST=Build and boot kunimitsu Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/16044 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Ibeb9a64824a71c253e45d6a1c6088abd737cf046 Reviewed-on: https://chromium-review.googlesource.com/368276 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> |
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| .. | ||
| broadcom/cygnus | ||
| dmp/vortex86ex | ||
| imgtec/pistachio | ||
| intel | ||
| marvell | ||
| mediatek/mt8173 | ||
| nvidia | ||
| qualcomm | ||
| rdc/r8610 | ||
| rockchip | ||
| samsung | ||
| ucb/riscv | ||