Michał Żygowski 940d1d0868 soc/intel/cannonlake: Let coreboot lock MSR_IA32_DEBUG_INTERFACE ... Intel TXT requires the debug interface to be disabled. There is no way to program the MSR_IA32_DEBUG_INTERFACE using FSP as needed, so let coreboot handle it. TEST=Boot Linux with tboot on Protectli VP4670 with Intel TXT enabled Change-Id: I7ed4382bbe68f03e8eca151245c13928609f434f Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>		2025-03-10 15:19:26 +00:00
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cpu_ids.h	soc/intel/xeon_sp/gnr: Move CPU ID definition to common header	2024-09-13 11:14:33 +00:00
em64t100_save_state.h
em64t101_save_state.h
fsb.h
l2_cache.h
microcode.h
msr.h	soc/intel/cannonlake: Let coreboot lock MSR_IA32_DEBUG_INTERFACE	2025-03-10 15:19:26 +00:00
post_codes.h
smm_reloc.h
speedstep.h
turbo.h