erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions
coreboot/src/cpu/intel
History
Sven Schnelle 8d846135ff ACPI: mark empty get_cst_entries() weak 
This function prevents the linker from choosing the right
get_cst_entries(), preventing writing the _CST tables.

Change-Id: I4bc0168aee110171faeaa081f217dfd1536bb821
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/496
Tested-by: build bot (Jenkins)
2012-01-09 11:07:18 +01:00
..
bga956 Rename build system variables to be more intuitive, and 2010-09-30 16:55:02 +00:00
car Remove XIP_ROM_BASE 2011-11-01 19:06:23 +01:00
ep80579 Rename build system variables to be more intuitive, and 2010-09-30 16:55:02 +00:00
hyperthreading Rename build system variables to be more intuitive, and 2010-09-30 16:55:02 +00:00
microcode Make update-microcodes.sh executable. 2010-10-18 00:20:40 +00:00
model_6bx Add missing Intel Pentium II/III era CPU IDs. 2010-10-04 20:43:55 +00:00
model_6dx update intel microcode files. 2010-10-18 00:21:39 +00:00
model_6ex Remove XIP_ROM_BASE 2011-11-01 19:06:23 +01:00
model_6fx Remove XIP_ROM_BASE 2011-11-01 19:06:23 +01:00
model_6xx update intel microcode files. 2010-10-18 00:21:39 +00:00
model_65x cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs. 2011-08-04 08:10:12 +02:00
model_67x cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs. 2011-08-04 08:10:12 +02:00
model_68x Add missing Intel Pentium II/III era CPU IDs. 2010-10-04 20:43:55 +00:00
model_69x update intel microcode files. 2010-10-18 00:21:39 +00:00
model_106cx Remove XIP_ROM_BASE 2011-11-01 19:06:23 +01:00
model_1067x factor out cpu power management base into a separate file. And fix a bug in 2010-12-11 22:14:44 +00:00
model_f0x drop unused files 2011-01-12 21:09:25 +00:00
model_f1x drop unused files 2011-01-12 21:09:25 +00:00
model_f2x Activate older Xeon P4 microcodes 2011-10-18 00:10:51 +02:00
model_f3x Remove some duplicate #include files (trivial). 2010-10-07 23:42:17 +00:00
model_f4x update intel microcode files. 2010-10-18 00:21:39 +00:00
slot_1 cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs. 2011-08-04 08:10:12 +02:00
slot_2 Drop unused DCACHE_RAM_BASE from intel/car/cache_as_ram.inc-using sockets. 2010-10-15 07:47:51 +00:00
socket_441 oops. this is weird. CAR addresses should be specified in the socket and not in 2011-01-27 01:11:20 +00:00
socket_FC_PGA370 Get rid of the old romstage-as-bootblock ROM layout 2011-10-28 22:17:36 +02:00
socket_mFCBGA479 Move "select CACHE_AS_RAM" lines from boards into CPU socket. 2010-12-08 08:22:04 +00:00
socket_mFCPGA478 oops. this is weird. CAR addresses should be specified in the socket and not in 2011-01-27 01:11:20 +00:00
socket_mPGA478 Rename build system variables to be more intuitive, and 2010-09-30 16:55:02 +00:00
socket_mPGA479M Move "select CACHE_AS_RAM" lines from boards into CPU socket. 2010-12-08 08:22:04 +00:00
socket_mPGA603 Rename build system variables to be more intuitive, and 2010-09-30 16:55:02 +00:00
socket_mPGA604 Rename build system variables to be more intuitive, and 2010-09-30 16:55:02 +00:00
socket_PGA370 Drop unused DCACHE_RAM_BASE from intel/car/cache_as_ram.inc-using sockets. 2010-10-15 07:47:51 +00:00
speedstep ACPI: mark empty get_cst_entries() weak 2012-01-09 11:07:18 +01:00
thermal_monitoring drop unused code (trivial) 2008-08-01 11:53:39 +00:00
Kconfig Move out Katmai Slot 1 CPUs (model_67x) from model_6xx to model_67x. 2010-10-13 17:00:42 +00:00
Makefile.inc Create new socket for FCPGA370 and PGA370 CPU's for CAR. Add CAR support for Coppermine FC-PGA CPU's (model_68x). 2010-06-21 19:40:09 +00:00