3134a81525
When cbmem is initialized in romstage and postcar placed in the stage
cache + cbmem where it is run, the assumption is made that these are
all in UC memory such that calling INVD in postcar is OK.
For performance reasons (e.g. postcar decompression) it is desirable
to cache cbmem and the stage cache during romstage.
Another reason is that AGESA sets up MTRR during romstage to cache all
dram, which is currently worked around by using additional MTRR's to
make that UC.
TESTED on asus/p5ql-em, up/squared on both regular and S3 resume
bootpath. Sometimes there are minimal performance improvements
when cbmem is cached (few ms).
Change-Id: I7ff2a57aee620908b71829457ea0f5a0c410ec5b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37196
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
238 lines
5.8 KiB
Text
238 lines
5.8 KiB
Text
if ARCH_X86
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config PARALLEL_MP
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def_bool y
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help
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This option uses common MP infrastructure for bringing up APs
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in parallel. It additionally provides a more flexible mechanism
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for sequencing the steps of bringing up the APs.
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The code also works for just initialising the BSP in case there
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are no APs.
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config PARALLEL_MP_AP_WORK
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def_bool n
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depends on PARALLEL_MP
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help
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Allow APs to do other work after initialization instead of going
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to sleep.
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config X86_SMM_SKIP_RELOCATION_HANDLER
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bool
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default n
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depends on PARALLEL_MP && HAVE_SMI_HANDLER
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help
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Skip SMM relocation using a relocation handler running in SMM
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with a stub at 0x30000. This is useful on platforms that have
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an alternative way to set SMBASE.
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config DEFAULT_X2APIC
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def_bool n
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help
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Allow SoC code to set LAPIC_ACCESS_MODE to X2APIC.
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config DEFAULT_X2APIC_RUNTIME
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def_bool n
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help
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Allow SoC code to set LAPIC_ACCESS_MODE to X2APIC_RUNTIME.
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config DEFAULT_X2APIC_LATE_WORKAROUND
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def_bool n
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help
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Allow SoC code to set LAPIC_ACCESS_MODE to X2APIC_LATE_WORKAROUND.
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choice LAPIC_ACCESS_MODE
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prompt "APIC operation mode"
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default X2APIC_ONLY if DEFAULT_X2APIC
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default X2APIC_RUNTIME if DEFAULT_X2APIC_RUNTIME
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default X2APIC_LATE_WORKAROUND if DEFAULT_X2APIC_LATE_WORKAROUND
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default XAPIC_ONLY
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config XAPIC_ONLY
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prompt "Set XAPIC mode"
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bool
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config X2APIC_ONLY
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prompt "Set X2APIC mode"
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bool
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depends on PARALLEL_MP
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config X2APIC_RUNTIME
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prompt "Support both XAPIC and X2APIC"
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bool
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depends on PARALLEL_MP
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config X2APIC_LATE_WORKAROUND
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prompt "Use XAPIC for AP bringup, then change to X2APIC"
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bool
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depends on PARALLEL_MP && MAX_CPUS < 256
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help
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Choose this option if the platform supports dynamic switching between
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XAPIC to X2APIC. The initial Application Processors (APs) are configured
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in XAPIC mode at reset and later enable X2APIC as a CPU feature.
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All access mechanisms between XAPIC (mmio) and X2APIC (msr) switches
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at runtime when this option is enabled.
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endchoice
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config UDELAY_LAPIC
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bool
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default n
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config LAPIC_MONOTONIC_TIMER
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def_bool n
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depends on UDELAY_LAPIC
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help
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Expose monotonic time using the local APIC.
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config UDELAY_LAPIC_FIXED_FSB
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int
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config UDELAY_TSC
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bool
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default n
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config UNKNOWN_TSC_RATE
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bool
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default y if LAPIC_MONOTONIC_TIMER
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config TSC_MONOTONIC_TIMER
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def_bool n
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depends on UDELAY_TSC
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help
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Expose monotonic time using the TSC.
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config TSC_SYNC_LFENCE
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bool
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default n
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help
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The CPU driver should select this if the CPU needs
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to execute an lfence instruction in order to synchronize
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rdtsc. This is true for all modern AMD CPUs.
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config TSC_SYNC_MFENCE
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bool
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default n
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help
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The CPU driver should select this if the CPU needs
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to execute an mfence instruction in order to synchronize
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rdtsc. This is true for all modern Intel CPUs.
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config SETUP_XIP_CACHE
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bool
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depends on !NO_XIP_EARLY_STAGES
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help
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Select this option to set up an MTRR to cache XIP stages loaded
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from the bootblock. This is useful on platforms lacking a
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non-eviction mode and therefore need to be careful to avoid
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eviction.
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config X86_CLFLUSH_CAR
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bool
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help
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Select this on platforms that allow CLFLUSH while operating in CAR.
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config HAVE_SMI_HANDLER
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bool
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default n
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depends on (SMM_ASEG || SMM_TSEG)
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config NO_SMM
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bool
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default n
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config SMM_ASEG
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bool
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default n
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depends on !NO_SMM
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config SMM_TSEG
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bool
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default y
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depends on !(NO_SMM || SMM_ASEG)
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if HAVE_SMI_HANDLER
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config SMM_MODULE_STACK_SIZE
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hex
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default 0x800 if ARCH_RAMSTAGE_X86_64
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default 0x400
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help
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This option determines the size of the stack within the SMM handler
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modules.
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endif
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config SMM_LAPIC_REMAP_MITIGATION
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bool
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default y if NORTHBRIDGE_INTEL_I945 || NORTHBRIDGE_INTEL_GM45 \
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|| NORTHBRIDGE_INTEL_X4X || NORTHBRIDGE_INTEL_PINEVIEW \
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|| NORTHBRIDGE_INTEL_E7505 || NORTHBRIDGE_INTEL_IRONLAKE
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default n
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config SMM_PCI_RESOURCE_STORE
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bool
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default n
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help
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This option enables support for storing PCI resources in SMRAM so
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SMM can tell if they've been altered.
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config SMM_PCI_RESOURCE_STORE_NUM_SLOTS
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int
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default 8
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help
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Number of slots available to store PCI BARs in SMRAM
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config X86_AMD_FIXED_MTRRS
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bool
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default n
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help
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This option informs the MTRR code to use the RdMem and WrMem fields
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in the fixed MTRR MSRs.
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config X86_INIT_NEED_1_SIPI
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bool
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default n
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help
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This option limits the number of SIPI signals sent during the
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common AP setup. Intel documentation specifies an INIT SIPI SIPI
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sequence, however this doesn't work on some AMD and Intel platforms.
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These newer AMD and Intel platforms don't need the 10ms wait between
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INIT and SIPI, so skip that too to save some time.
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config SOC_SETS_MSRS
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bool
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default n
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help
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The SoC requires different access methods for reading and writing
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the MSRs. Use SoC specific routines to handle the MSR access.
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config RESERVE_MTRRS_FOR_OS
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bool
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default n
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help
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This option allows a platform to reserve 2 MTRRs for the OS usage.
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The Intel SDM documents that the first 6 MTRRs are intended for
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the system BIOS and the last 2 are to be reserved for OS usage.
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However, modern OSes use PAT to control cacheability instead of
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using MTRRs.
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config AP_STACK_SIZE
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hex
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default 0x800
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help
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This is the amount of stack each AP needs. The BSP stack size can be
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larger and is set with STACK_SIZE.
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config RUNTIME_CONFIGURABLE_SMM_LOGLEVEL
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bool
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default n
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depends on DEBUG_SMI && CONSOLE_OVERRIDE_LOGLEVEL
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help
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This enables setting the SMM console log level at runtime for more
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flexibility to use different log levels for each stage. Another reason
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is that reading the log level from non-volatile memory such as flash
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VPD or CMOS is not very ideal to be done in SMM, with this option the
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value can be passed via the member variable in struct smm_runtime and
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be referenced directly in SMM.
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endif # ARCH_X86
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