PLT_RST_L was asserted twice at boot-up and a glitch was observed
when coming out of suspend mode. Configure PLT_RST_L pad IOSSTATE
from HIZCRx1 to be masked.
BRANCH=octopus
BUG=b:117302959
TEST=Verified no glitch on PLT_RST_L at S3 and PLT_RST_L stays high
3.3v during S0ix.
Change-Id: I8c23aadda72be54fb45e67aab2bc8ed51e473bae
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30815
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
8cf6d4d7d6