Arthur Heymans 8c740b08a3 lib/coreboot_table: Rename lb_fill_pcie ... By convention 'fill_lb_xxx' is used. Change-Id: I046016b3898308bb56b4ad6a5834ab942fdd50f2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69183 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2022-11-04 19:17:49 +00:00
..
acpi	acpigen: export acpigen_write_field_name	2022-11-02 21:03:40 +00:00
arch	treewide: Add 'IWYU pragma: export' comment	2022-11-03 13:05:17 +00:00
commonlib	commonlib: Fix AMD MP2 BUFFER id	2022-11-04 01:06:12 +00:00
console	console/post.c: Sort includes	2022-10-27 15:46:39 +00:00
cpu	Revert "cpu/x86/mp_init.c: Set a bogus initial lapic_id"	2022-11-03 23:57:41 +00:00
device	device/dram: Add kconfig options for memory types	2022-11-04 00:54:25 +00:00
drivers	lib/coreboot_table: Simplify API to set up lb_serial	2022-11-04 19:17:13 +00:00
ec	ec/google/wilco: Include <cpu/cpu.h> instead of <arch/cpu.h>	2022-11-03 13:01:43 +00:00
include	lib/coreboot_table: Rename lb_fill_pcie	2022-11-04 19:17:49 +00:00
lib	lib/coreboot_table: Rename lb_fill_pcie	2022-11-04 19:17:49 +00:00
mainboard	lib/coreboot_table: Simplify API to set up lb_serial	2022-11-04 19:17:13 +00:00
northbridge	nb/intel/pineview: Specify supported memory types	2022-11-04 00:57:00 +00:00
sbom	Add SBOM (Software Bill of Materials) Generation	2022-08-22 14:48:46 +00:00
security	security/memory/memory.h: Add <stdbool.h>	2022-10-06 17:01:52 +00:00
soc	lib/coreboot_table: Rename lb_fill_pcie	2022-11-04 19:17:49 +00:00
southbridge	treewide: Add 'IWYU pragma: export' comment	2022-11-03 13:05:17 +00:00
superio	superio/ite/common/early_serial.c: ite_kill_watchdog: set timeout to 0	2022-08-07 19:54:43 +00:00
vendorcode	vc/amd/fsp: Add Glinda directory	2022-10-27 22:22:16 +00:00
Kconfig	Kconfig: Allow x86 to compress pre-ram stages if not run XIP	2022-10-20 14:48:05 +00:00