Fred Reitberger fdb0758256 soc/amd/common/block/apob/apob_cache.c: Add assert for APOB DRAM size ... Add static check to ensure the reserved APOB DRAM space is the same size as the MRC_CACHE region specified in the fmap. Update sabrina APOB DRAM size to match the fmap. TEST: Timeless builds identical. Test build with a larger MRC_CACHE than APOB DRAM failed the assert as expected. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ia14f6ef94b9062df0612fe96098b1012085ccf9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65878 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2022-08-01 20:44:09 +00:00
..
acpi
arch	arch/x86/acpi: Replace Store() with ASL 2.0 syntax	2022-07-30 00:11:58 +00:00
commonlib	commonlib: compiler.h: Use non-concise comment style	2022-07-28 12:32:56 +00:00
console
cpu	arch/x86: Fix MAX_CPUS check proper for late X2APIC config	2022-07-25 10:06:18 +00:00
device
drivers	drivers/elog: Use format string	2022-08-01 09:27:50 +00:00
ec
include	include: Add SPDX-License-Identifiers to files missing them	2022-08-01 13:59:11 +00:00
lib
mainboard	mb/google/herobrine: Add PCIe domain support	2022-08-01 18:04:54 +00:00
northbridge	nb/amd: Fix some white spaces issues	2022-07-17 21:57:31 +00:00
security	security/vboot: Simplify image signing	2022-07-30 18:29:25 +00:00
soc	soc/amd/common/block/apob/apob_cache.c: Add assert for APOB DRAM size	2022-08-01 20:44:09 +00:00
southbridge	sb/intel/bd82x6x/acpi: Replace LEqual(a,b) with ASL 2.0 syntax	2022-07-29 10:16:25 +00:00
superio
vendorcode	Revert "UPSTREAM: soc/amd/sabrina,vc/amd/fsp/sabrina: Add UART support for Sabrina"	2022-08-01 12:36:31 +00:00
Kconfig