coreboot/src
Daniel Kurtz 8a6377ec24 mb/google/kahlee: Do not define SIO_EC_ENABLE_COM1
This #define tells superio.asl to add a "PNP0501" "Plug and Play
16550A-compatible COM port" entry to kahlee's ACPI tables.

The EC on kahlee boards do not provide a "Serial Port 1" that should
be exposed via ACPI to the OS.  In fact, this entry confuses the
kernel and in some cases can cause it to try to redirect output to a
non existing port.

BUG=b:74200887
TEST=Deploy to grunt.  Boot kernel with SERIAL_PORT_DFNS undefined and
 "earlycon=uart,mmio32,0xfedc6000,115200,48000000" on the kernel
 command line, and with an image with serial console enabled.
 => System boots with (kernel) serial console enabled, starting from
    0.00 (earlycon), with no gaps in its output, and serial console
    also allows logging in.

Change-Id: I0eaed9b4461bb6a6c1aa4ce97752f588d4322b35
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/25021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-03-08 19:04:03 +00:00
..
acpi arch/x86: Add common AMD ACPI hardware definitions 2017-11-10 19:15:38 +00:00
arch smbios: Extend Baseboard (or Module) Information (type2) 2018-03-07 21:12:47 +00:00
commonlib timestamps: Add timestamps around the vbios load & init 2018-03-08 18:14:54 +00:00
console console: only allow console messages after initialization 2018-03-02 15:22:24 +00:00
cpu cpu/x86/mp_init: Increase AP check-in time-out to 1second 2018-03-05 17:55:44 +00:00
device timestamps: Add timestamps around the vbios load & init 2018-03-08 18:14:54 +00:00
drivers drivers/intel/fsp2_0: Fix build error while DISPLAY_HOBS is selected 2018-02-28 17:40:01 +00:00
ec ec/google/chromeec: Fix typo preventing PD EC firmware inclusion 2018-03-07 12:12:38 +00:00
include smbios: Extend Baseboard (or Module) Information (type2) 2018-03-07 21:12:47 +00:00
lib coreboot_table: Print GPIO state correctly for lb_gpios 2018-03-08 17:55:23 +00:00
mainboard mb/google/kahlee: Do not define SIO_EC_ENABLE_COM1 2018-03-08 19:04:03 +00:00
northbridge nb/intel/haswell: Generate ACPI DMAR table 2018-03-08 17:49:50 +00:00
security security/vboot: overwrite existing spaces during factory init for tpm2 2018-02-07 02:37:25 +00:00
soc soc/intel/common/block/gspi: set cs polarity before using 2018-03-08 18:24:05 +00:00
southbridge sb/intel/common: Fix conflicting OIC register definition 2018-03-02 17:21:06 +00:00
superio Intel i3100 boards & chips: Remove - using LATE_CBMEM_INIT 2018-01-15 23:25:12 +00:00
vendorcode intel/fsp: Update cannonlake fsp header 2018-02-14 17:01:25 +00:00
Kconfig smbios: Add option to select the enclosure type 2018-03-01 13:46:49 +00:00