Duncan Laurie 89bbe146cb mb/google/volteer: Add fw_config entries for boot device ... Add the fw_config entries for the newly added boot device fields. These are added as separate fields since a board may have more than one selected. BUG=b:173129299 TEST=abuild google/volteer Change-Id: I2af9ffcf0b90d4f4b7f2f31613ee110d8f350454 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>		2020-12-02 16:31:44 +00:00
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acpi	src/acpi/acpigen: Add NULL pointer check	2020-12-02 06:07:05 +00:00
arch	arch/x86/car.ld: Check for out of bound on no-XIP stages	2020-12-02 10:41:00 +00:00
commonlib	cbfs: Add metadata cache	2020-11-21 10:43:53 +00:00
console
cpu	cpu/x86/early_reset: Mark assemblycode as 32bit	2020-12-01 16:00:40 +00:00
device	device: Drop unused HyperTransport code	2020-11-25 09:11:46 +00:00
drivers	drivers/aspeed/common/ast: Fix compilation under x86_64	2020-12-01 16:01:31 +00:00
ec	ec/google/chromeec/acpi: Make OperationRegion brace align	2020-12-01 08:00:23 +00:00
include	include/device/pci_ids.h: Fix device id for gspi2	2020-11-30 08:07:00 +00:00
lib	lib/reg_script: Add cast to fix compilation on x86_64	2020-12-01 16:00:57 +00:00
mainboard	mb/google/volteer: Add fw_config entries for boot device	2020-12-02 16:31:44 +00:00
northbridge	nb/amd: Deduplicate nb_common.h	2020-11-25 09:11:58 +00:00
security	cbfs: Add metadata cache	2020-11-21 10:43:53 +00:00
soc	soc/amd/picasso: add FSP binary location	2020-12-02 15:21:09 +00:00
southbridge	soc/amd/common: introduce SOC_AMD_COMMON_BLOCK_PCI_MMCONF	2020-11-30 16:27:52 +00:00
superio	superio/smsc/sio1036: Support 16-bit IO port addressing	2020-11-18 13:12:11 +00:00
vendorcode	vendorcode/intel/fsp: Add Elkhart Lake FSP headers for FSP v2341	2020-12-02 10:44:57 +00:00
Kconfig