Nico Huber 8885529e15 soc/intel/apl: Configure LPC serial IRQ mode ... Sync the FSP settings with what coreboot does. Why both FSP and coreboot configure this redundantly stays a secret. TEST=Set SERIRQ_CONTINUOUS on kontron/mal10. A CPLD connected to LPC works correctly now, but was confused by the wrong settings before because the FSP defaults allowed to disable the LPC clock. Change-Id: Id1c7180f460678bf0f9458228591050dd628c052 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/29901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>		2018-12-03 06:10:39 +00:00
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apollolake	soc/intel/apl: Configure LPC serial IRQ mode	2018-12-03 06:10:39 +00:00
baytrail	cpu/intel/common: Use a common acpi/cpu.asl file	2018-11-30 22:02:35 +00:00
braswell	cpu/intel/common: Use a common acpi/cpu.asl file	2018-11-30 22:02:35 +00:00
broadwell	cpu/intel/common: Use a common acpi/cpu.asl file	2018-11-30 22:02:35 +00:00
cannonlake	cpu/intel/common: Use a common acpi/cpu.asl file	2018-11-30 22:02:35 +00:00
common	soc/intel/common: Rework acpi/cpu.asl	2018-11-30 21:53:00 +00:00
denverton_ns	cpu/intel/common: Use a common acpi/cpu.asl file	2018-11-30 22:02:35 +00:00
fsp_baytrail	cpu/intel/common: Use a common acpi/cpu.asl file	2018-11-30 22:02:35 +00:00
fsp_broadwell_de	arch/acpi.h: Add some update to version 6.2a	2018-11-29 12:21:03 +00:00
icelake	cpu/intel/common: Use a common acpi/cpu.asl file	2018-11-30 22:02:35 +00:00
quark	{mb/cubieboard,soc/intel/quark}: Remove define __SIMPLE_DEVICE__	2018-11-29 12:20:16 +00:00
skylake	cpu/intel/common: Use a common acpi/cpu.asl file	2018-11-30 22:02:35 +00:00
Kconfig	src/cpu: Remove dead sourced lines	2018-11-15 10:25:20 +00:00