coreboot/src/soc
Barnali Sarkar 05df2c6661 UPSTREAM: soc/intel/skylake: Correct address of I2C5 Device
This corrects the address of the I2C5 Device. The I2C
Controller #5 is on PCI Bus 0: Device 25: Function 1. The ACPI
Address Encoding Logic is - High word = Device #.
                            Low word = Function #.
So, I2C5 (_ADR) = 0x0019 0001.

BUG=none
BRANCH=none
TEST=Build and boot kunimitsu

Change-Id: I67b639c99b2fd6a549ec6fb3cbb3666e82bf37a6
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/16048
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/368364
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
2016-08-11 20:39:47 -07:00
..
broadcom/cygnus UPSTREAM: Remove non-ascii & unprintable characters 2016-08-05 11:45:20 -07:00
dmp/vortex86ex UPSTREAM: src/soc: Capitalize CPU, ACPI, RAM and ROM 2016-08-04 23:37:59 -07:00
imgtec/pistachio drivers/uart: Use uart_platform_refclk for all UART models 2016-05-09 18:45:44 +02:00
intel UPSTREAM: soc/intel/skylake: Correct address of I2C5 Device 2016-08-11 20:39:47 -07:00
marvell UPSTREAM: src/soc: Capitalize CPU, ACPI, RAM and ROM 2016-08-04 23:37:59 -07:00
mediatek/mt8173 UPSTREAM: Remove extra newlines from the end of all coreboot files. 2016-08-04 23:36:56 -07:00
nvidia chromeos: Make CHROMEOS_RAMOOPS_NON_ACPI a default for non-ACPI boards 2016-08-10 22:16:49 -07:00
qualcomm soc/qualcomm/ipq40xx: Reduce the delay in I2C. 2016-08-08 20:19:59 -07:00
rdc/r8610 rdc/r8610: Move to src/soc 2016-05-05 20:08:58 +02:00
rockchip Revert "rockchip: rk3399: enable sdhci clk for emmc" 2016-08-10 13:09:47 -07:00
samsung UPSTREAM: src/soc: Capitalize CPU, ACPI, RAM and ROM 2016-08-04 23:37:59 -07:00
ucb/riscv UPSTREAM: arch/riscv: Move CBMEM into RAM 2016-07-15 08:39:35 -07:00