coreboot/src
Martin Roth 8845759a02 vendorcode/intel/fsp/baytrail/absf: add Minnow Max absf files
The absf files contain the modifications to the default settings in
the FSP.  They are used as input files for Intel's 'Binary Configuration
Tool' (BCT) along with the FSP.bin file to generate customized FSP
binaries.

The Minnow Max absf files set up the values for the soldered down
memory.  This requirement will go away with the release of the next
Bay Trail FSP, and the memory settings will be configurable at
runtime.

Change-Id: Id72545d78a7e82d9a5090710a9c7a8a9b1e81208
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/6432
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-08-11 20:52:12 +02:00
..
arch coreboot classes: Add dynamic classes to coreboot 2014-08-11 15:42:20 +02:00
console src/console/Kconfig: Fix choice for showing POST codes on console 2014-07-30 20:34:08 +02:00
cpu x86/smm/smihandler.c: break case in switch 2014-08-11 17:03:45 +02:00
device device/oprom/realmode: Sanitize header inclusion 2014-08-08 03:32:13 +02:00
drivers drivers: Add I2C TPM driver to coreboot 2014-08-10 22:25:48 +02:00
ec lenovo/h8: Remove useless smi.h include. 2014-08-11 00:46:33 +02:00
include coreboot_tables: reduce redundant data structures 2014-08-10 22:23:19 +02:00
lib coreboot classes: Add dynamic classes to coreboot 2014-08-11 15:42:20 +02:00
mainboard bayleybay_fsp: Add bakersport board variant 2014-08-11 20:06:44 +02:00
northbridge gm45: Declare brightness variables for ACPI use. 2014-08-11 19:10:29 +02:00
soc soc/intel/fsp_baytrail: set up for including irqroute.h twice 2014-08-11 07:22:58 +02:00
southbridge i82801ix: Declare gen decode registers. 2014-08-11 09:12:29 +02:00
superio superio/smsc/sio1036: Clean up RAMstage superio.c component 2014-08-09 10:06:13 +02:00
vendorcode vendorcode/intel/fsp/baytrail/absf: add Minnow Max absf files 2014-08-11 20:52:12 +02:00
Kconfig drivers: Add I2C TPM driver to coreboot 2014-08-10 22:25:48 +02:00