coreboot/src/soc/intel
Felix Singer 88264ef30b soc/intel/skylake: Add IMGU definitions to pci_devs.h
Change-Id: Iee7393ae7e2aca94151c242894c64ac902f4d437
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-08-08 12:00:39 +00:00
..
apollolake {nb,soc}/intel: Use get_current_microcode_rev() for ucode version 2020-08-05 15:36:38 +00:00
baytrail {sb,soc}/intel/*/acpi/lpc.asl: Drop commented-out code 2020-08-05 15:46:17 +00:00
braswell {sb,soc}/intel/*/acpi/lpc.asl: Drop commented-out code 2020-08-05 15:46:17 +00:00
broadwell soc/intel/broadwell/iobp: Log success in pch_iobp_write() 2020-08-07 11:57:32 +00:00
cannonlake soc/intel/cnl: Set Heci1Disable depending on devicetree config 2020-08-07 20:35:29 +00:00
common soc/intel/common: Log CSE FW Status Registers before triggering recovery 2020-08-07 08:30:35 +00:00
denverton_ns cpu,soc/intel: Drop select SMP 2020-07-26 20:59:52 +00:00
icelake soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE 2020-08-07 06:05:12 +00:00
jasperlake soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE 2020-08-07 06:05:12 +00:00
quark src: Make HAVE_CF9_RESET set the FADT reset register 2020-07-20 13:23:13 +00:00
skylake soc/intel/skylake: Add IMGU definitions to pci_devs.h 2020-08-08 12:00:39 +00:00
tigerlake soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE 2020-08-07 06:05:12 +00:00
xeon_sp xeon_sp/cpx: Enable HWP Intel Speed Shift 2020-08-07 12:37:04 +00:00
Kconfig fsp2_0: Gather Kconfig declarations 2020-04-05 23:26:24 +00:00