Alexandru Gagniuc 86f6a135a1 mainboard/intel: Add skeleton for Apollolake RVP board family ... RVP1 board comes with DDR3 SODIMMs and discrete VRs. RVP2 board uses LPDDR3 and PMIC. Change-Id: I3e47c157c49ad55ff1ba824672ac2630a64a6037 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13298 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)		2016-02-11 21:10:30 +01:00
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acpi	acpi/: add missing license header	2016-01-14 22:52:11 +01:00
arch	arch/x86: Change how BOOTBLOCK_CUSTOM is selected by default	2016-02-11 06:22:08 +01:00
commonlib	commonlib: move uefi includes out of commonlib includes	2016-02-02 14:27:03 +01:00
console	console: Disable SQUELCH_EARLY_SMP if SMP is not selected	2016-02-09 17:14:50 +01:00
cpu	cpu/x86/tsc: Compile delay_tsc.c for the bootblock as well	2016-02-11 19:21:24 +01:00
device	arch/x86: Drop arch/pciconf.h	2016-01-26 20:22:44 +01:00
drivers	intel/fsp1_0: Allow the MRC cache to live in a FMAP region	2016-02-10 16:27:12 +01:00
ec	ASL: Remove unused modulo recipient.	2016-02-09 22:56:00 +01:00
include	cpu/intel/microcode: allow microcode to be loaded in romstage	2016-02-10 18:08:28 +01:00
lib	nhlt: add api to override oem_id and oem_table_id of acpi_header_t	2016-02-09 13:21:39 +01:00
mainboard	mainboard/intel: Add skeleton for Apollolake RVP board family	2016-02-11 21:10:30 +01:00
northbridge	Kconfig: Move defaults for CBFS_SIZE	2016-02-10 16:27:50 +01:00
soc	soc/apollolake: Add initial cache-as-ram setup for bootblock	2016-02-11 21:00:07 +01:00
southbridge	Kconfig: Move defaults for CBFS_SIZE	2016-02-10 16:27:50 +01:00
superio	superio/nuvoton/nct5572d: Add PS/2 presence detect	2016-02-09 20:34:15 +01:00
vendorcode	chromeos/Kconfig: Remove dependency on GBB_HAVE_BMPFV	2016-02-10 16:53:55 +01:00
Kconfig	Kconfig: Move defaults for CBFS_SIZE	2016-02-10 16:27:50 +01:00