Ronak Kanabar 16da569df9 vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2237_00 ... The headers added are generated as per FSP v2237_00. Previous FSP version was v2207_01. Changes Include: - Add VccInAuxImonIccImax in FspsUpd.h - Adjust Reserved UPD Offset in FspmUpd.h and FspsUpd.h - Few UPDs description update in FspmUpd.h and FspsUpd.h BUG=b:192199787 BRANCH=None TEST=Build and boot brya Change-Id: Ie291204a3fa0b9451c418c84bd40a17ef08a436c Cq-Depend:chrome-internal:3970327,chrome-internal:3925290 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55896 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-07-13 15:14:56 +00:00
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amd	vc/amd/sb800: Cast to UINT32 for shift out of bounds fix	2021-07-12 07:32:24 +00:00
cavium	src: use ARRAY_SIZE where possible	2021-02-15 11:30:40 +00:00
eltan	vc/eltan/security/mboot/Kconfig: Add dependency of VBOOT	2021-04-06 07:01:31 +00:00
google	timestamp,vc/google/chromeos/cr50: Add timestamp for enable update	2021-07-05 10:50:06 +00:00
intel	vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2237_00	2021-07-13 15:14:56 +00:00
mediatek	vc/mediatek/mt8195: Remove redundant code	2021-07-13 01:46:30 +00:00
siemens	cbfs: Simplify load/map API names, remove type arguments	2020-12-02 22:13:17 +00:00
Makefile.inc	soc/mediatek/mt8192: initialize DRAM using vendor reference code	2021-03-08 03:15:43 +00:00