coreboot/src
Zheng Bao 861f920cdf AMD/Mullins: Fix the interrupt routing
The plugged devices on PCIe should use IOAPIC2 instead of standard
IOAPIC1. The entries in IOAPIC2 count from the end of IOAPIC1.
The unchanged code worked because the OS uses MSI instead APIC.
To test that, boot linux with parameter pci=nomsi and see if the devices
like NIC work well as they do without the booting parameter.
run 'cat /proc/interrupts' to see if devices actually use
no-msi.

Change-Id: I5eab28956b7a3fbc7c10447e99d6c11dbe6a1d14
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/12363
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-11-12 09:26:08 +01:00
..
acpi tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
arch cpu/amd: Add CC6 support 2015-11-11 18:45:14 +01:00
commonlib commonlib: Remove unused static function. 2015-11-09 12:26:31 +01:00
console arm64: remove secmon 2015-11-07 03:28:06 +01:00
cpu cpu/amd: Add CC6 support 2015-11-11 18:45:14 +01:00
device tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
drivers [REMOVAL] drivers/trident/blade3d 2015-11-10 20:23:36 +01:00
ec tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
include cpu/amd: Add CC6 support 2015-11-11 18:45:14 +01:00
lib arm/arm64: Generalize bootblock C entry point 2015-11-11 05:08:07 +01:00
mainboard AMD/Mullins: Fix the interrupt routing 2015-11-12 09:26:08 +01:00
northbridge northbridge/amd/amdmct: Verify MCT NVRAM options before skipping training 2015-11-12 00:51:23 +01:00
soc fsp_baytrail: Add macros for legacy GPIO output set up 2015-11-11 06:42:01 +01:00
southbridge southbridge/amd/sb700: Add option to disable SATA ALPM 2015-11-12 00:56:26 +01:00
superio Drop SuperIO fintek/f71889 2015-11-10 20:16:49 +01:00
vendorcode southbridge/intel: Add FSP based i89xx southbridge support 2015-11-10 00:00:46 +01:00
Kconfig arm/arm64: Generalize bootblock C entry point 2015-11-11 05:08:07 +01:00