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coreboot/src/soc/intel
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Matt DeVillier 859a781705 soc/intel/cannonlake: Add/use chipset devicetrees 
Change-Id: I8ceae832e60cd3094b4a34ab3a279e5a011f2c80
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-26 18:01:29 +00:00
..
alderlake device/device.h: Rename pci_domain_scan_bus 2023-10-20 14:24:57 +00:00
apollolake soc/intel/apollolake: Select USE_LEGACY_8254_TIMER 2023-10-26 10:24:43 +00:00
baytrail x86: Add pre-memory stages CBFS cache scratchpad support 2023-10-20 14:32:44 +00:00
braswell x86: Add pre-memory stages CBFS cache scratchpad support 2023-10-20 14:32:44 +00:00
broadwell device/device.h: Rename pci_domain_scan_bus 2023-10-20 14:24:57 +00:00
cannonlake soc/intel/cannonlake: Add/use chipset devicetrees 2023-10-26 18:01:29 +00:00
common cbmem.h: Drop cbmem_possible_online in favor of ENV_HAS_CBMEM 2023-10-25 13:58:02 +00:00
denverton_ns device/device.h: Rename pci_domain_scan_bus 2023-10-20 14:24:57 +00:00
elkhartlake device/device.h: Rename pci_domain_scan_bus 2023-10-20 14:24:57 +00:00
jasperlake device/device.h: Rename pci_domain_scan_bus 2023-10-20 14:24:57 +00:00
meteorlake soc/intel/meteorlake: Add PsysPmax configuration 2023-10-24 17:59:29 +00:00
skylake device/device.h: Rename pci_domain_scan_bus 2023-10-20 14:24:57 +00:00
tigerlake soc/intel/tigerlake: Add ACPI devices for FSPI, SRAM, HEC1 2023-10-23 20:59:36 +00:00
xeon_sp soc/intel/xeon_sp/spr: Add SATA controllers 1 and 2 to devicetree 2023-10-13 13:51:50 +00:00
Makefile.inc soc/intel/Makefile.inc: Add comment where CONFIG_CSE_*_FILE are used 2023-09-22 15:48:08 +00:00