Frans Hendriks 83e7324969 soc/intel/braswell/ramstage.c: Add SoC stepping D-1 support ... No support for SoC D-1 stepping is available. According to Intel doc #332095-015 stepping C-0 has revision id 0x21 and D-1 revision ID 0x35. Also correct the RID_C_STEPPING_START value for C-0. BUG=none TEST=Built, Intel Cherry Hill Rev F. Change-Id: I29268f797f68aa4e3b6203e098485e0bd4a44fc4 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/27471 Reviewed-by: Wim Vervoorn Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2018-09-21 14:14:10 +00:00
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apollolake	soc/intel/denverton_ns: Enable common block PMC	2018-09-14 14:11:03 +00:00
baytrail	src/*/intel/: clarify Kconfig options regarding IFD	2018-09-13 08:25:31 +00:00
braswell	soc/intel/braswell/ramstage.c: Add SoC stepping D-1 support	2018-09-21 14:14:10 +00:00
broadwell	soc/broadwell: Don't use device_t	2018-09-21 14:05:04 +00:00
cannonlake	soc/intel/cannonlake: Correct ITSS port id.	2018-09-21 02:21:40 +00:00
common	soc/intel/common/block: Don't use device_t in ramstage	2018-09-18 10:49:06 +00:00
denverton_ns	soc/intel/denverton_ns: Enable common block PMC	2018-09-14 14:11:03 +00:00
fsp_baytrail	src/*/intel/: clarify Kconfig options regarding IFD	2018-09-13 08:25:31 +00:00
fsp_broadwell_de	soc/intel/fsp_broadwell_de: Add fixed VT-d MMIO range to the resources	2018-09-20 12:38:49 +00:00
quark	soc/intel/quark/uart.c: Don't use device_t	2018-09-21 14:12:42 +00:00
skylake	soc/intel/skylake: Don't use device_t	2018-09-21 14:05:22 +00:00
Kconfig	Kconfig: Add config to insert ucode address in second FIT	2018-07-19 08:07:49 +00:00