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coreboot/src/cpu/intel/car
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Kyösti Mälkki 823020d56b intel i945 gm45 x4x post-car: Use postcar_frame for MTRR setup 
Adapt implementation from skylake to prepare for removal of
HIGH_MEMORY_SAVE and moving on to RELOCATABLE_RAMSTAGE.
With this change, CBMEM region is set early-on as WRBACK
with MTRRs and romstage ram stack is moved to CBMEM.

Change-Id: Idee5072fd499aa3815b0d78f54308c273e756fd1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15791
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-11 08:57:17 +01:00
..
cache_as_ram.inc intel car: Remove guard on XIP_ROM_SIZE 2016-07-22 05:39:03 +02:00
cache_as_ram_ht.inc intel i945 gm45 x4x post-car: Use postcar_frame for MTRR setup 2016-12-11 08:57:17 +01:00
romstage.c intel i945 gm45 x4x post-car: Use postcar_frame for MTRR setup 2016-12-11 08:57:17 +01:00
romstage_legacy.c intel post-car: Split legacy sockets 2016-11-08 19:46:25 +01:00