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Subrata Banik 8104effa0d mainboard/intel/tglrvp: Remove unused PrmrrSize chip config 
Refer to commit 7736bfc

TEST=Able to build and boot TGLRVP.

Change-Id: Ie9a97cee7d7793077167db3a642dcbca45b09427
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43139
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09 12:44:26 +00:00
..
acpi acpigen: Add acpigen_notify 2020-07-07 20:31:22 +00:00
arch arch/x86: Add memmove.c to x86 bootblock 2020-07-08 21:06:47 +00:00
commonlib lib/coreboot_table: Add Intel FSP version to coreboot table 2020-07-04 11:20:08 +00:00
console
cpu haswell: relocate romstage_common to northbridge 2020-07-08 22:16:58 +00:00
device
drivers dptf: Add support for IDSP 2020-07-07 17:23:47 +00:00
ec ec/google: Add function ec_fill_dptf_helpers() 2020-07-07 20:31:30 +00:00
include ACPI: Add and fill gnvs_ptr for smm_runtime 2020-07-08 07:32:51 +00:00
lib lib: Temporarily remove timestamps from psp_verstage 2020-07-08 19:37:50 +00:00
mainboard mainboard/intel/tglrvp: Remove unused PrmrrSize chip config 2020-07-09 12:44:26 +00:00
northbridge haswell: relocate romstage_common to northbridge 2020-07-08 22:16:58 +00:00
security security/vboot: Allow files to go into only RW-A or RW-B region 2020-07-08 19:36:24 +00:00
soc mainboard/intel/tglrvp: Remove unused PrmrrSize chip config 2020-07-09 12:44:26 +00:00
southbridge sb/intel/lynxpoint: Program PM registers directly 2020-07-08 22:26:15 +00:00
superio
vendorcode vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww26 release and adapt soc 2020-07-07 22:24:41 +00:00
Kconfig arch/x86: Remove RELOCATABLE_RAMSTAGE 2020-07-06 06:17:47 +00:00