coreboot/src
Raul E Rangel 80d042c467 soc/amd: Print dimm_info and TYPE17_DMI_INFO to help debug incorrect values
Example output:
AGESA TYPE 17 DMI INFO:
  Handle: 1
  TotalWidth: 64
  DataWidth: 64
  MemorySize: 8192
  DeviceSet: 0
  Speed: 1200
  ManufacturerIdCode: 44416
  Attributes: 1
  ExtSize: 0
  ConfigSpeed: 933
  MemoryType: 0x1a
  FormFactor: 0xd
  DeviceLocator:   DIMM 0
  BankLocator:  CHANNEL A
  SerialNumber(8):  00000000
  PartNumber(20): HMAA51S6AMR6N-UH

CBMEM_ID_MEMINFO:
  dimm_size: 0
  ddr_type: 0x1a
  ddr_frequency: 1200
  rank_per_dimm: 1
  channel_num: 0
  dimm_num: 0
  bank_locator: 0
  mod_id: 44416
  mod_type: 0x1a
  bus_width: 64
  serial(4): 0000
  module_part_number(23): HMAA51S6AMR6N-UH   ��@

dimm_size, mod_type, bus_width need to be updated so they return the
correct values. module_part_number is missing a null terminator due to
the AGESA part number being larger than the dimm_info buffer.

Example dmidecode output:
Memory Device
        Array Handle: 0x0000
        Error Information Handle: Not Provided
        Total Width: 8 bits
        Data Width: 8 bits
        Size: No Module Installed
        Form Factor: Unknown
        Set: None
        Locator: Channel-0-DIMM-0
        Bank Locator: BANK 0
        Type: DDR4
        Type Detail: Synchronous
        Speed: 1200 MT/s
        Manufacturer: Hynix/Hyundai
        Serial Number: 0000
        Asset Tag: Not Specified
        Part Number: HMAA51S6AMR6N-UH
        Rank: 1
        Configured Clock Speed: 1200 MT/s
        Minimum Voltage: Unknown
        Maximum Voltage: Unknown
        Configured Voltage: Unknown

To enable the output set CONFIG_DEBUG_RAM_SETUP.

The Kconfig change is required in order to enable
CONFIG_DEBUG_RAM_SETUP, otherwise it's not a valid option.

BUG=b:65403853
TEST=Test output shown above

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5eac00b9400056357915761287770a400b3f9f8b
Reviewed-on: https://review.coreboot.org/25303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-23 15:33:27 +00:00
..
acpi arch/x86: Add common AMD ACPI hardware definitions 2017-11-10 19:15:38 +00:00
arch arch/x86/smbios: Strip trailing whitespace on DMI 17 part number. 2018-03-23 15:33:16 +00:00
commonlib timestamps: Add timestamps around the vbios load & init 2018-03-08 18:14:54 +00:00
console console: only allow console messages after initialization 2018-03-02 15:22:24 +00:00
cpu cpu/x86/mp_init: Print amount of time it takes in bsp_do_flight_plan 2018-03-09 00:26:30 +00:00
device src/device/dram/ddr2: Fix supported burst lengths 2018-03-14 11:17:42 +00:00
drivers drivers/i2c/designware: Fix indentation 2018-03-21 15:56:55 +00:00
ec ec/google/chromeec: Add boardid.c to bootblock 2018-03-09 12:40:10 +00:00
include include: Update dimm_info documentation 2018-03-23 15:33:09 +00:00
lib Timestamps: Add option to print timestamps to debug console 2018-03-09 17:16:21 +00:00
mainboard mainboard/intel/cannonlake_rvp: Enable S0ix 2018-03-23 08:56:34 +00:00
northbridge nb/intel/haswell;sb/intel/lynxpoint: Enable VT-d and X2APIC 2018-03-08 19:14:17 +00:00
security security/tpm: Fix TPM software stack vulnerability 2018-03-16 04:13:26 +00:00
soc soc/amd: Print dimm_info and TYPE17_DMI_INFO to help debug incorrect values 2018-03-23 15:33:27 +00:00
southbridge nb/intel/haswell;sb/intel/lynxpoint: Enable VT-d and X2APIC 2018-03-08 19:14:17 +00:00
superio Intel i3100 boards & chips: Remove - using LATE_CBMEM_INIT 2018-01-15 23:25:12 +00:00
vendorcode vendorcode/intel: Update FSP Header files per v2.0.0 2018-03-23 01:23:14 +00:00
Kconfig Timestamps: Add option to print timestamps to debug console 2018-03-09 17:16:21 +00:00