7f8afe0631
Certain chipsets don't have a memory-mapped boot media so their code execution for stages prior to DRAM initialization is backed by SRAM or cache-as-ram. The postcar stage/phase handles the cache-as-ram situation where in order to tear down cache-as-ram one needs to be executing out of a backing store that isn't transient. By current definition, cache-as-ram is volatile and tearing it down leads to its contents disappearing. Therefore provide a shim layer, postcar, that's loaded into memory and executed which does 2 things: 1. Tears down cache-as-ram with a chipset helper function. 2. Loads and runs ramstage. Because those 2 things are executed out of ram there's no issue of the code's backing store while executing the code that tears down cache-as-ram. The current implementation makes no assumption regarding cacheability of the DRAM itself. If the chipset code wishes to cache DRAM for loading of the postcar stage/phase then it's also up to the chipset to handle any coherency issues pertaining to cache-as-ram destruction. Change-Id: Ia58efdadd0b48f20cfe7de2f49ab462306c3a19b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14140 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
81 lines
2.4 KiB
C
81 lines
2.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2003 Eric Biederman
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef CONSOLE_CONSOLE_H_
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#define CONSOLE_CONSOLE_H_
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#include <stdint.h>
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#include <rules.h>
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#include <console/post_codes.h>
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#include <commonlib/loglevel.h>
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#ifndef __ROMCC__
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struct console_driver {
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void (*init)(int);
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void (*tx_byte)(int, unsigned char byte);
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void (*tx_flush)(int);
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unsigned char (*rx_byte)(int);
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int (*tst_byte)(void);
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};
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void post_code(u8 value);
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#if CONFIG_CMOS_POST_EXTRA
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void post_log_extra(u32 value);
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struct device;
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void post_log_path(struct device *dev);
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void post_log_clear(void);
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#else
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#define post_log_extra(x) do {} while (0)
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#define post_log_path(x) do {} while (0)
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#define post_log_clear() do {} while (0)
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#endif
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/* this function is weak and can be overridden by a mainboard function. */
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void mainboard_post(u8 value);
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void __attribute__ ((noreturn)) die(const char *msg);
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#define __CONSOLE_ENABLE__ \
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((ENV_BOOTBLOCK && CONFIG_BOOTBLOCK_CONSOLE) || \
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ENV_VERSTAGE || ENV_ROMSTAGE || ENV_RAMSTAGE || ENV_POSTCAR || \
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(ENV_SMM && CONFIG_DEBUG_SMI))
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#if __CONSOLE_ENABLE__
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void console_init(void);
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int console_log_level(int msg_level);
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int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));
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void do_putchar(unsigned char byte);
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#define printk(LEVEL, fmt, args...) \
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do { do_printk(LEVEL, fmt, ##args); } while(0)
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#else
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static inline void console_init(void) {}
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static inline int console_log_level(int msg_level) { return 0; }
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static inline void printk(int LEVEL, const char *fmt, ...) {}
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static inline void do_putchar(unsigned char byte) {}
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#endif
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#if CONFIG_CHROMEOS
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/* FIXME: Collision of varargs with AMD headers without guard. */
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#include <console/vtxprintf.h>
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#if __CONSOLE_ENABLE__
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void do_printk_va_list(int msg_level, const char *fmt, va_list args);
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#else
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static inline void do_printk_va_list(int l, const char *fmt, va_list args) {}
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#endif
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#endif
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#endif /* !__ROMCC__ */
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#endif /* CONSOLE_CONSOLE_H_ */
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