coreboot/src
Alexandru Gagniuc 7efd5fda49 hp/pavilion_m6_1035dx: Map USB and PWRB PME sources to GPE 11
Hudson ASL files assume the USB power event notifications are mapped
to GPE 0xb. Since that GPE is not used on this board, map these events
to GPE11. This GPE is already handled in ACPI via Method(_L0B). We
adjust this method to also notify the XHCI controller at PCI 10:0.

Change-Id: If33dd4bb5830820227f7c8b34594886cfae37282
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5554
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-21 21:32:43 +02:00
..
arch build rules: Identify build stage with simple variables 2014-04-18 16:40:32 +02:00
console console: Simplify the enable rules 2014-04-18 16:41:09 +02:00
cpu Move MAX_PHYSICAL_CPUS to AMD k8 and fam10 2014-04-20 20:04:07 +02:00
device OxPCIe uart: Split PCI bridge control 2014-04-09 11:29:45 +02:00
drivers console: Drop driver list in ramstage 2014-04-18 16:39:09 +02:00
ec ec/compal/ene932: Update to use coreboot EC-mainboard API 2014-04-19 03:49:48 +02:00
include drivers/elog: Fix implicit function declaration issue 2014-04-20 17:43:34 +02:00
lib rmodule: add subsections to linker script 2014-04-19 07:11:41 +02:00
mainboard hp/pavilion_m6_1035dx: Map USB and PWRB PME sources to GPE 11 2014-04-21 21:32:43 +02:00
northbridge AMD AGESA fam15tn/fam16kb: Remove unused source files 2014-04-16 14:39:11 +02:00
soc console: Move newline translation outside console_tx_byte 2014-04-09 13:21:25 +02:00
southbridge AMD hudson and yangtze boards: Let mainboard declare power button 2014-04-21 21:32:34 +02:00
superio superio/ite/it8728f: Fix headers and prototype location 2014-04-15 04:35:20 +02:00
vendorcode vendorcode/amd/agesa/fam14: Build as a static library 2014-04-15 17:23:37 +02:00
Kconfig buildsystem: check for coreboot toolchain by default 2014-04-16 08:20:06 +02:00