0365fc8186
Use a read modify write sequence when setting the SPI_USE_SPI100 bit in the SPI100_ENABLE register. This avoids clearing other bits in the register which might cause instabilities. Haven't checked the reference code, but the register descriptions suggested that the register in Mullins behaves similar to the one in Stoneyridge. Right now this code is unused, but it's probably still a good idea to fix it. TEST=Booting Debian 11 with kernel 5.10 on apu2 still works when adding a call to hudson_set_spi100 with this patch applied. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifbd960a9509542b28f03326a3066995540260bef Tested-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> |
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