coreboot/src
Aaron Durbin 7ddb5f76fe tegra132: Add Trust Zone register access
The Trust Zone carveout registers are only accessible using
a secure access mode. The AVP runs as non-secure all the time.
In EL3 the CPU is in secure mode, but when the MMU is enabled
the page tables dictate if accesses to certain regions are
secure or not. However, ramstage is currently being loaded
into non-secure memory and the page tables will live in
non-secure memory as well. Therefore, handle all these
cases by providing global state which mirrors the TZ
register.

BUG=chrome-os-partner:30782
BRANCH=None
TEST=Built and ran through ramstage with the MMU enabled
     Resources are read and set accordingly.

Original-Change-Id: Ib76b2641497a29ef2adb75934b2df55ecf0b3e78
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/209061
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 0bcbdc5697)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I9c1beed443a48870ba190427e87caf90caf4ff6b
Reviewed-on: http://review.coreboot.org/8648
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-13 00:15:55 +01:00
..
arch armv8: Add mmu support 2015-03-13 00:11:00 +01:00
console console/Kconfig: Enable CBMEM console by default 2015-03-10 23:42:22 +01:00
cpu x86 SMM: Replace weak prototypes with weak function stub 2015-03-11 18:15:22 +01:00
device AMD fam10: Drop PCI_BUS_SEGN_BITS 2015-03-09 19:33:08 +01:00
drivers drivers/i2c/w83793: Use devicetree.cb to set additional values 2015-02-26 06:20:07 +01:00
ec acpi: Generate valid ACPI processor objects 2015-02-16 21:02:30 +01:00
include x86 SMM: Replace weak prototypes with weak function stub 2015-03-11 18:15:22 +01:00
lib Add and consistently use wrapper macro for romstage static variables 2015-03-09 22:42:28 +01:00
mainboard ryu: Add TPS65913 regs/init for VDD_CPU 1.0V 2015-03-13 00:10:33 +01:00
northbridge ACPI: Get S3 resume state from romstage_handoff 2015-03-10 23:42:10 +01:00
soc tegra132: Add Trust Zone register access 2015-03-13 00:15:55 +01:00
southbridge x86 SMM: Replace weak prototypes with weak function stub 2015-03-11 18:15:22 +01:00
superio superio/fintek/f81216h: Add the correct unlock key values 2015-02-14 00:53:26 +01:00
vendorcode Add and consistently use wrapper macro for romstage static variables 2015-03-09 22:42:28 +01:00
Kconfig nvram: Add option to reset NVRAM to default parameters on every boot 2015-02-16 08:36:37 +01:00