coreboot/src/soc/intel
Wenkai Du f10b368e01 broadwell: add RCBA posting read after writing
MEI PCI device has internal logic to flush out the posted writes
before returning completion for non-posted request. When doing a RCBA
write to function disable and then using the PCI CFG RD cycle, need
to do RCBA posting read after writing to it to make sure the write
went through.

As Aaron sugegsted, abstracted function disable path to a common
function.

BUG=chrome-os-partner:33048
TEST=run warm and cold reboot testing

Change-Id: I87aa8ccd604446263fc3621c9a01839a5a75b644
Signed-off-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/223715
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2014-10-17 01:14:19 +00:00
..
baytrail baytrail: Switch from ACPI mode to PCI mode for legacy support 2014-09-26 20:16:14 +00:00
broadwell broadwell: add RCBA posting read after writing 2014-10-17 01:14:19 +00:00
common baytrail: Move HDA verb table to Intel SOC common directory 2014-04-23 02:47:34 +00:00
Kconfig broadwell: Hook into the build system 2014-05-15 05:15:08 +00:00
Makefile.inc broadwell: Hook into the build system 2014-05-15 05:15:08 +00:00