coreboot/src
Duncan Laurie 7d55ce2c25 cmos post: Guard with spinlock
The CMOS post code storage mechanism does back-to-back
CMOS reads and writes that may be interleaved during
CPU bringup, leading to corruption of the log or of other
parts of CMOS.

BUG=chrome-os-partner:19980
BRANCH=none
TEST=manual: verify post codes in CMOS during suspend/resume test

Change-Id: I704813cc917a659fe034b71c2ff9eb9b80f7c949
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/58102
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2013-06-10 18:08:22 -07:00
..
arch cmos post: Guard with spinlock 2013-06-10 18:08:22 -07:00
console cmos post: Guard with spinlock 2013-06-10 18:08:22 -07:00
cpu ec: Add romstage function for checking and rebooting EC 2013-06-04 12:53:44 -07:00
device device tree: track init times 2013-05-01 15:36:25 -07:00
drivers RTC: Skip rtc_init() in S3 resume path 2013-05-28 13:50:07 -07:00
ec slippy/falco/peppy: Enable SERIRQ continuous mode 2013-06-04 12:53:46 -07:00
include Drop ELF remains from boot code 2013-05-28 13:50:06 -07:00
lib Drop ELF remains from boot code 2013-05-28 13:50:06 -07:00
mainboard slippy: update verbs for ALC283 2013-06-05 10:33:59 -07:00
northbridge haswell: Update pei_data to match ref code 2013-06-04 12:53:42 -07:00
southbridge lynxpoint: Enable USB clock gating, late setup, and sleep prep 2013-06-03 14:33:47 -07:00
superio Drop prototype guarding for romcc 2013-05-10 11:55:20 -07:00
vendorcode vboot: use out_flags to indicate recovery mode 2013-06-04 12:53:47 -07:00
Kconfig BACKPORT: x86: add thread support 2013-05-15 11:19:50 -07:00