Kyösti Mälkki 6ef93e607c UPSTREAM: AGESA vendorcode: Build a common amdlib ... Having CFLAGS with -Os disables -falign-function, for unlucky builds this may delay entry to ramstage by 600ms. Build the low-level IO functions aligned with -O2 instead. Change-Id: Ice6781666a0834f1e8e60a0c93048ac8472f27d9 Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com> Original-Reviewed-on: https://review.coreboot.org/14414 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry-picked from commit 08311f5033) Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/346627 Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2016-05-26 03:21:31 -07:00
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allwinner	drivers/uart: Use uart_platform_refclk for all UART models	2016-05-09 18:45:44 +02:00
amd	UPSTREAM: AGESA vendorcode: Build a common amdlib	2016-05-26 03:21:31 -07:00
armltd	vboot2: add verstage	2015-01-27 01:41:40 +01:00
dmp	x86 chipsets: Link non-code flow CHIPSET_BOOTBLOCK_INCLUDE files	2015-12-30 18:34:08 +01:00
intel	{cpu,soc}/intel: remove unused smm_init() function	2016-05-06 16:48:21 +02:00
qemu-power8	cpu/qemu-power8: don't enable it for qemu-x86	2016-02-19 20:03:52 +01:00
qemu-x86	qemu-x86: Enable SMP support	2015-12-08 15:54:27 +01:00
ti	drivers/uart: Use uart_platform_refclk for all UART models	2016-05-09 18:45:44 +02:00
via	cpu/via/c7: Don't manually include udelay_io.c	2016-03-10 16:56:23 +01:00
x86	UPSTREAM: intel/sch: Merge northbridge and southbridge in src/soc	2016-05-20 17:08:20 -07:00
Kconfig	cpu: Add a way to use microcode .h files back to the build	2015-11-10 19:22:40 +01:00
Makefile.inc	cpu: Add a way to use microcode .h files back to the build	2015-11-10 19:22:40 +01:00