coreboot/src/soc
Patrick Rudolph 7c8de869a2 soc/intel/cannonlake: Enable wake from USB in S4
The xHCI controller supports waking the system from S1-S4.
Thus specify that the deepest sleep state is S4 in _PRW.

Tested on Prodrive/hermes. The board now wakes from S4 as well by
pressing a key on the USB keyboard.

Change-Id: I0bb266e70ee6b4eb8922671b7d0078db0d29a1da
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49224
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-11 07:33:13 +00:00
..
amd ACPI: Drop redundant ChromeOS setup for GNVS 2021-01-10 11:16:55 +00:00
cavium cbfs: Simplify load/map API names, remove type arguments 2020-12-02 22:13:17 +00:00
example arch/x86: Move prologue to .init section 2021-01-07 11:02:03 +00:00
intel soc/intel/cannonlake: Enable wake from USB in S4 2021-01-11 07:33:13 +00:00
mediatek soc/mediatek: rtc: Use bool as return type 2021-01-07 02:02:51 +00:00
nvidia Makefile: Add $(xcompile) to specify where to write xcompile 2020-12-23 03:40:35 +00:00
qualcomm cbfs: Simplify load/map API names, remove type arguments 2020-12-02 22:13:17 +00:00
rockchip drivers: Replace set_vbe_mode_info_valid 2020-12-17 06:21:56 +00:00
samsung cbfs: Enable CBFS mcache on most chipsets 2020-12-02 22:12:10 +00:00
sifive cbfs: Enable CBFS mcache on most chipsets 2020-12-02 22:12:10 +00:00
ti cbfs: Enable CBFS mcache on most chipsets 2020-12-02 22:12:10 +00:00
ucb soc/ucb/riscv: Add chip_operations stub 2020-05-28 09:30:35 +00:00