coreboot/src/soc/intel
Julius Werner 7c712bbb6c Fix code that would trip -Wtype-limits
This patch fixes up all code that would throw a -Wtype-limits warning.
This sometimes involves eliminating unnecessary checks, adding a few odd
but harmless casts or just pragma'ing out the warning for a whole file
-- I tried to find the path of least resistance. I think the overall
benefit of the warning outweighs the occasional weirdness.

Change-Id: Iacd37eb1fad388d9db7267ceccb03e6dcf1ad0d2
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32537
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-06 10:32:15 +00:00
..
apollolake vboot: refactor OPROM code 2019-04-30 21:47:25 +00:00
baytrail vboot: refactor OPROM code 2019-04-30 21:47:25 +00:00
braswell soc/intel/braswell/Makefile.inc: Remove commented-out line 2019-05-06 10:29:13 +00:00
broadwell Fix code that would trip -Wtype-limits 2019-05-06 10:32:15 +00:00
cannonlake soc/intel/cannonlake: Add GPIO dual-route support. 2019-05-06 10:27:17 +00:00
common soc/skylake: Add missing PCH IDs 2019-05-06 10:29:02 +00:00
denverton_ns soc/intel: Add GPI interrupt config register offset info 2019-04-29 12:18:27 +00:00
fsp_baytrail src: Use include <console/console.h> when appropriate 2019-04-23 10:01:21 +00:00
fsp_broadwell_de soc/{amd,intel}/chip: Use local include for chip.h 2019-04-26 16:49:13 +00:00
icelake soc/intel/icelake: Correct the GPE DWx mapping for GPIO groups 2019-05-02 06:03:21 +00:00
quark soc/{amd,intel}/chip: Use local include for chip.h 2019-04-26 16:49:13 +00:00
skylake soc/skylake: Add missing PCH IDs 2019-05-06 10:29:02 +00:00
Kconfig src/cpu: Remove dead sourced lines 2018-11-15 10:25:20 +00:00