Arthur Heymans 74f9fe6e58 cpu/intel/car/non-evict: Select NO_FIXED_XIP_ROM_SIZE ... CPU's featuring a non eviction mode cache the whole ROM. Therefore XIP stages don't need to follow some alignment constraints. Change-Id: I4a30f31baa0f90279c0690ceb6aefea6de461bd9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>		2019-04-25 15:56:28 +00:00
..
allwinner	src: Use #include <timer.h> when appropriate	2019-04-06 16:02:49 +00:00
amd	src: Add missing include 'console.h'	2019-04-23 10:00:39 +00:00
armltd	vboot2: add verstage	2015-01-27 01:41:40 +01:00
intel	cpu/intel/car/non-evict: Select NO_FIXED_XIP_ROM_SIZE	2019-04-25 15:56:28 +00:00
qemu-power8	arch/power8: Rename to ppc64	2018-11-30 20:02:17 +00:00
qemu-x86	bootblock: Move function prototype	2018-12-30 11:32:08 +00:00
ti	cpu/ti/am335x: Fix checkpatch warnings	2019-04-01 07:54:40 +00:00
via	src: Add required space after "switch"	2018-11-19 08:17:06 +00:00
x86	cpu/x86: Move checking for MTRR's as a proxy for proper CPU reset	2019-04-21 23:29:29 +00:00
Kconfig	arch/x86: Drop Kconfig AP_SIPI_VECTOR	2019-01-13 08:37:01 +00:00
Makefile.inc	Untangle CBFS microcode updates	2019-01-10 09:24:02 +00:00