coreboot/src/cpu
Aaron Durbin 7c35131642 haswell: configure c-states
The c-states are configured according to the BWG, however the
package c-states are disabled as they currently cause platform
instability. The exposed ACPI c-state to processor c-state mapping
are as follows for ULT boards:
	ACPI(C1) = MWAIT(C1E)
	ACPI(C2) = MWAIT(C7S long latency)
	ACPI(C3) = MWAIT(C10)
The non-ULT boards have an expoed c-state mapping:
	ACPI(C1) = MWAIT(C1E)
	ACPI(C2) = MWAIT(C3)
	ACPI(C3) = MWAIT(C7S)

Included in this patch is removing the updating of current limit
registers as some of the MSRs are different and the proper values
are currently unknown. Lastly, some of the MSRs were renamed to
match the BWG.

Booted 3.8 kernel and used powertop to note package, core, and acpi
c-state residency.

Change-Id: Ia428d4a4979ba3cba44eb9faa96f74b7d3f22dfe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48291
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4133
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24 16:01:38 +01:00
..
amd vendorcode/amd/agesa/f16kb: Update Kabini PI from v1.0.0.0 to v1.0.0.7 2013-10-15 05:01:11 +02:00
armltd ARMv7: De-uboot-ify Exynos5250 code 2013-07-10 20:08:15 +02:00
dmp dmp/vortex86ex: Move DMP specific POST code defines into one file 2013-11-24 05:36:36 +01:00
intel haswell: configure c-states 2013-11-24 16:01:38 +01:00
qemu-x86 qemu: add q35 support 2013-06-17 17:04:17 +02:00
samsung exynos5420: Fix build warning 2013-09-28 22:25:14 +02:00
ti am335x: Update the config vars selected by CPU_TI_AM335X. 2013-09-17 00:41:01 +02:00
via cpu: Fix spelling 2013-07-11 22:36:59 +02:00
x86 smi: Update mainboard_smi_gpi() to have 32bit argument 2013-11-24 07:40:22 +01:00
Kconfig Make EARLY_CONSOLE optional 2013-08-07 19:12:48 +02:00
Makefile.inc cpu: Add CPU microcode file to cbfs with 16-byte alignment 2013-07-10 21:45:28 +02:00